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Yosys Update -> v0.42 #2596

Merged
merged 1 commit into from
Jul 8, 2024
Merged

Yosys Update -> v0.42 #2596

merged 1 commit into from
Jul 8, 2024

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amirarjmand93
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@amirarjmand93 amirarjmand93 commented Jun 7, 2024

Description

This update brings Yosys to the latest version, 0.42, which includes several bug fixes, performance improvements, and new features that enhance the synthesis capabilities of our flow. Notable additions in this version include :
-New commands and options
-Verific support
-Added support for using the ABCs library
-Added support for VHDL 2009
...

For a detailed list of changes and improvements in Yosys 0.42 (June 7, 2024), please refer to the release notes.

Related Issue

-Update Yosys [The latest version in the VTR flow is 0.32]

Types of changes

  • New feature (change which adds functionality)
  • I have added tests to cover my changes
  • All new and existing tests passed

@github-actions github-actions bot added lang-cpp C/C++ code lang-python Python code lang-make CMake/Make code lang-hdl Hardware Description Language (Verilog/VHDL) lang-shell Shell scripts (bash etc.) Parmys labels Jun 7, 2024
@vaughnbetz
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Thanks @amirarjmand93

  1. There are some CI failures. E.g. in vtr_nightly_test1 there are many QoR failures on very small arithmetic designs due to wider channel widths. This is likely OK; we could fix them by checking in new golden results. We could also evaluate widening the QoR tolerance for them. There is at least one circuit that just failed to complete though, so it should be looked at:

vtr_reg_nightly_test1/arithmetic_tasks/figure_8...[Fail]
2024-06-07T16:02:32.7292766Z �[32;1m16:02:32�[0m | [Fail]
2024-06-07T16:02:32.7294215Z �[32;1m16:02:32�[0m | fixed_k6_frac_2ripple_N8_22nm.xml/adder_006bits.v/common min_chan_width_routing_area_total relative value 0.6611539867743371 outside of range [0.7,1.3] and not equal to golden value: 503264.0
2024-06-07T16:02:32.7295848Z �[32;1m16:02:32�[0m | [Fail]
2024-06-07T16:02:32.7297283Z �[32;1m16:02:32�[0m | fixed_k6_frac_2ripple_N8_22nm.xml/adder_006bits.v/common min_chan_width_routing_area_per_tile relative value 0.6611519467095439 outside of range [0.7,1.3] and not equal to golden value: 1741.4
2024-06-07T16:02:32.7298818Z �[32;1m16:02:32�[0m | [Fail]
2024-06-07T16:02:32.7300223Z �[32;1m16:02:32�[0m | fixed_k6_frac_2ripple_N8_22nm.xml/adder_006bits.v/common crit_path_routing_area_total relative value 0.6711054902544265 outside of range [0.7,1.3] and not equal to golden value: 618332.0
2024-06-07T16:02:32.7301669Z �[32;1m16:02:32�[0m | [Fail]
2024-06-07T16:02:32.7303074Z �[32;1m16:02:32�[0m | fixed_k6_frac_2ripple_N8_22nm.xml/adder_006bits.v/common crit_path_routing_area_per_tile relative value 0.6711052739815663 outside of range [0.7,1.3] and not equal to golden value: 2139.56
2024-06-07T16:02:32.7304516Z �[32;1m16:02:32�[0m |
2024-06-07T16:02:32.7305189Z �[32;1m16:02:32�[0m | vtr_reg_nightly_test1/arithmetic_tasks/figure_8...[Fail]
2024-06-07T16:02:32.7305948Z �[32;1m16:02:32�[0m | [Fail]
2024-06-07T16:02:32.7307276Z �[32;1m16:02:32�[0m | fixed_k6_frac_2ripple_N8_22nm.xml/adder_011bits.v/common min_chan_width relative value 1.3076923076923077 outside of range [0.25,1.3] and not equal to golden value: 26.0
2024-06-07T16:02:32.7308835Z �[32;1m16:02:32�[0m |
2024-06-07T16:02:32.7309521Z �[32;1m16:02:32�[0m | vtr_reg_nightly_test1/arithmetic_tasks/figure_8...[Fail]
2024-06-07T16:02:32.7310328Z �[32;1m16:02:32�[0m | [Fail]
2024-06-07T16:02:32.7311705Z �[32;1m16:02:32�[0m | fixed_k6_frac_2uripple_N8_22nm.xml/adder_005bits.v/common vpr_status Task value 'exited with return code 2' does not match golden 'success'

  1. You should get a QoR spreadsheet on the VTR designs and Koios vs. the master, and attach it to this PR. We need to check that QoR is OK before merging.

@amirarjmand93
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amirarjmand93 commented Jun 8, 2024

Thanks for your attention @vaughnbetz .
After reviewing the log files, I found two major failures during the build process and testing( excluding the out-of-range failure test).

Errors:

[Run-tests (vtr_reg_nightly_test1, 16)]

  • fixed_k6_frac_2uripple_N8_22nm/adder_005bits Error: Executable vpr failed

[Run-tests (parmys_reg_strong, 16, -DYOSYS_F4PGA_PLUGINS=ON)]

  • [ 65%] Performing build step for 'f4pga-plugins'
    2024-06-07T14:22:29.3974673Z �[31;1m14:22:29�[0m | CMake Error at /root/vtr-verilog-to-routing/vtr-verilog-to-routing/build/libs/EXTERNAL/f4pga-plugins/src/f4pga-plugins-stamp/f4pga-plugins-build-release.cmake:37 (message):
    2024-06-07T14:22:29.3976625Z �[31;1m14:22:29�[0m | Command failed: 2

I will debug it.


Quick Update 1

[Run-tests (vtr_reg_nightly_test1, 16)]

command :
time -v /home/amir/vtr/vtr-verilog-to-routing/vpr/vpr fixed_k6_frac_2uripple_N8_22nm.xml adder_005bits --circuit_file adder_005bits.pre-vpr.blif --routing_failure_predictor off --seed 1 --min_route_chan_width_hint 28 --max_router_iterations 150 --route --route_chan_width 24

  • I found an error in vpr.crit_path.out :
  • Circuit is unroutable with a channel width factor of 24.
  • VPR failed to implement circuit.

Solution:
I changed the channel width factor to 26 and it worked fine(VPR succeeded/Exit status: 0).

@amirarjmand93
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amirarjmand93 commented Jun 8, 2024

Quick Update 2

[Run-tests (parmys_reg_strong, 16, -DYOSYS_F4PGA_PLUGINS=ON)]

f4pga-plugins conflict with Yosys v0.42 [building error]

command:
make -k CMAKE_PARAMS=-DYOSYS_F4PGA_PLUGINS=ON -j16

  • The f4pga-plugins encountered a compilation error due to missing or incorrect member references in the UhdmAst.cc file(in yosys-f4gpa-plugins).

  • The errors were related to the structure Yosys::AST::AstNode that did not have the member "multirange_dimensions".

  • multirange_dimensions vector member has been replaced with dimensions vector in recent Yosys updates( v0.39 and later)

possibly, The last Yosys version compatible with f4pga-plugins is v0.38 ( I've checked. it still use multirange_dimensions vector)

can see these changes in v0.32(current) and v0.42 of Yosys here:

https://github.com/search?q=repo%3Averilog-to-routing%2Fvtr-verilog-to-routing+yosys%2Ffrontends%2Fast+multirange_dimensions&type=code

https://github.com/search?q=repo%3AYosysHQ%2Fyosys+frontends%2Fast+dimensions&type=code

@vaughnbetz
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Thanks @amirarjmand93 . Can you change f4pga-plugins to use the new dimensions vector?

@amirarjmand93
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I've noticed that this modification isn't just a simple name change. In summary, "multirange_dimensions" and "dimensions" serve different purposes in the code snippets. "multirange_dimensions" is used to store range or dimension-related values, while "dimensions" is used to store dimension-specific information as tuples or objects.

  • I opened an issue in yosys-f4pga-plugins and commented about the problem and existing mismatch with recent yosys versions. It seems that their repository has not been updated for a long time.

@vaughnbetz
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Thanks. I suspect raising an issue in yosys is also a good idea.
Let's discuss who the owner is of f4pga-plugins is in the meeting today, and if we should upgrade to a slightly older yosys version to avoid breaking f4pga-plugins for now.
We could alternatively drop the CI test for f4pga plugins if it is not being used. I suspect it would be better to do that after the vtr9 release though so there is a code drop that will support it for some time.

@amirarjmand93 amirarjmand93 mentioned this pull request Jun 17, 2024
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@amirarjmand93
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amirarjmand93 commented Jun 25, 2024

@vaughnbetz i provided these spreadsheets for tasks which have gotten QoR failures .

list of QoR failure tasks:

 vtr_reg_nightly_test1/arithmetic_tasks/open_cores
 vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/
 vtr_reg_nightly_test1/ arithmetic_tasks/figure_8/
 
 vtr_reg_nightly_test1/ power_extended_arch_list

 vtr_reg_nightly_test3/vtr_reg_qor_chain_depop

 vtr_reg_nightly_test4/koios_medium 

 vtr_reg_strong/strong_two_chains

 vtr_reg_strong/strong_blocks_with_no_inputs

 ./run_reg_test.py parmys_reg_basic -show_failures -j2[?? searching to find a solution for comparing new result and golden result ]

arithmetic_tasks/figure_8/:

Metric Yosys v32 Yosys v42
vtr_flow_elapsed_time 1 0.878751541
odin_synth_time
parmys_synth_time 1 0.828800862
abc_depth 1 1
abc_synth_time 1 0.921552249
num_clb 1 1
num_memories
num_mult
max_vpr_mem 1 0.981665328
num_pre_packed_blocks 1 1
num_post_packed_blocks 1 1
device_grid_tiles 1 1
pack_time 1 0.845874978
placed_wirelength_est 1 0.96744725
place_time 1 0.689834314
placed_CPD_est 1 1.000659305
min_chan_width 1 0.999665495
routed_wirelength 1 0.990064679
min_chan_width_route_time 1 0.726366862
crit_path_routed_wirelength 1 0.972588016
critical_path_delay 1 0.994119577
geomean_nonvirtual_intradomain_critical_path_delay 1 0.994119577
crit_path_route_time 1 0.682706921

arithmetic_tasks/multless_consts/:

Metric Yosys v32 Yosys v42
vtr_flow_elapsed_time 1 0.869821165
odin_synth_time
parmrys_synth_time 1 0.830019347
abc_depth 1 1
abc_synth_time 1 0.971507169
num_clb 1 0.999878511
num_memories
num_mult
max_vpr_mem 1 0.987511139
num_pre_packed_blocks 1 1.000019055
num_post_packed_blocks 1 0.999965019
device_grid_tiles 1 1
pack_time 1 0.86419852
placed_wirelength_est 1 0.998035703
place_time 1 0.604457231
placed_CPD_est 1 0.999131431
min_chan_width 1 1.003640423
routed_wirelength 1 0.999289254
min_chan_width_route_time 1 0.983098221
crit_path_routed_wirelength 1 0.997210788
critical_path_delay 1 1.004301609
geomean_nonvirtual_intradomain_critical_path_delay 1 1.004301609
crit_path_route_time 1 0.593429341

arithmetic_tasks/open_cores/:

Metric Yosys v32 Yosys v42
vtr_flow_elapsed_time 1 1.113606582
odin_synth_time
parmys_synth_time 1 0.679979309
abc_depth 1 1
abc_synth_time 1 0.609705498
num_clb 1 0.993078614
num_memories
num_mult
max_vpr_mem 1 1.041184351
num_pre_packed_blocks 1 0.998703817
num_post_packed_blocks 1 0.997823691
device_grid_tiles 1 0.968729306
pack_time 1 0.710540536
placed_wirelength_est 1 0.977015642
place_time 1 0.586874684
placed_CPD_est 1 1.00466634
min_chan_width 1 0.961582986
routed_wirelength 1 0.971579281
min_chan_width_route_time 1 2.062185503
crit_path_routed_wirelength 1 0.0905131
critical_path_delay 1 1.019147316
geomean_nonvirtual_intradomain_critical_path_delay 1 1.019147316
crit_path_route_time 1 0.494861046

power_extended_arch_list:

Metric Yosys v32 Yosys v42
vtr_flow_elapsed_time 1 0.866953042
odin_synth_time
parmrys_synth_time 1 0.849716581
abc_depth 1 1.002724809
abc_synth_time 1 0.853781707
num_clb 1 1.007387763
num_memories 1 1
num_mult 1 1
max_vpr_mem 1 0.971571523
num_pre_packed_blocks 1 1.007979095
num_post_packed_blocks 1 1.001785019
device_grid_tiles 1 1
pack_time 1 0.92705389
placed_wirelength_est 1 1.016607824
place_time 1 0.745145613
placed_CPD_est 1 1.025607617
min_chan_width 1 0.975936204
routed_wirelength 1 1.024286909
min_chan_width_route_time 1 0.919461012
crit_path_routed_wirelength 1 1.015019107
critical_path_delay 1 0.992633418
geomean_nonvirtual_intradomain_critical_path_delay 1 0.992633418
crit_path_route_time 1 0.690175505

vtr_reg_nightly_test3/vtr_reg_qor_chain_depop:

Metric Yosys v32 Yosys v42
vtr_flow_elapsed_time 1 0.5296606
odin_synth_time
parmys_synth_time 1 0.637773292
abc_depth 1 0.985912618
abc_synth_time 1 0.564587073
num_clb 1 0.992202967
num_memories 1 1
num_mult 1 1
max_vpr_mem 1 0.966119897
num_pre_packed_blocks 1 0.999331696
num_post_packed_blocks 1 0.999766007
device_grid_tiles 1 1.001851053
pack_time 1 0.675008133
placed_wirelength_est 1 1.005892102
place_time 1 0.533514049
placed_CPD_est 1 1.014534348
min_chan_width 1 0.472035677
routed_wirelength 1 1.018252024
min_chan_width_route_time 1 0.472035677
crit_path_routed_wirelength 1 1.005619849
critical_path_delay 1 1.004742284
geomean_nonvirtual_intradomain_critical_path_delay 1 1.005394682
crit_path_route_time 1 0.597452232

vtr_reg_strong/strong_two_chains:

Metric Yosys v32 Yosys v42
vtr_flow_elapsed_time 1 0.805609915
odin_synth_time
parmys_synth_time 1 1.181818182
abc_depth 1 1
abc_synth_time 1 0.846153846
num_clb 1 0.8
num_memories
num_mult
max_vpr_mem 1 1.010545942
num_pre_packed_blocks 1 1.005772006
num_post_packed_blocks 1 0.979381443
device_grid_tiles 1 1
pack_time 1 1.909090909
placed_wirelength_est 1 0.953508581
place_time 1 0.756097561
placed_CPD_est 1 1.040465533
min_chan_width 1 1.033333333
routed_wirelength 1 0.890721649
min_chan_width_route_time 1 0.685688406
crit_path_routed_wirelength 1 0.481
critical_path_delay 1 1.042376196
geomean_nonvirtual_intradomain_critical_path_delay 1 1.042376196
crit_path_route_time 1 0.760869565

vtr_reg_strong/strong_blocks_with_no_inputs:

Metric Yosys v32 Yosys v42
vtr_flow_elapsed_time 1 0.80420254
odin_synth_time
parmys_synth_time 1 0.761423258
abc_depth 1 1
abc_synth_time 1 0.894288155
num_clb 1 0.987011517
num_memories 1 1
num_mult 1 1
max_vpr_mem 1 0.987537275
num_pre_packed_blocks 1 1.004517018
num_post_packed_blocks 1 0.998408905
device_grid_tiles 1 1
pack_time 1 0.673314855
placed_wirelength_est 1 0.967036028
place_time 1 0.506331949
placed_CPD_est 1 1.02934466
min_chan_width 1 1.023626599
routed_wirelength 1 0.937117394
min_chan_width_route_time 1 0.766880309
crit_path_routed_wirelength 1 0.96694093
critical_path_delay 1 1.000926603
geomean_nonvirtual_intradomain_critical_path_delay 1 1.001235661
crit_path_route_time 1 0.649704458

vtr_reg_nightly_test4/koios_medium:

Metric Yosys v32 Yosys v42
vtr_flow_elapsed_time 1 0.811111458
odin_synth_time
parmys_synth_time 1 0.745504074
abc_depth 1 1
abc_synth_time 1 0.680231734
num_clb 1 1.004558871
num_memories 1 1
num_mult
max_vpr_mem 1 1.016084213
num_pre_packed_blocks 1 0.999448692
num_post_packed_blocks 1 1.005645151
device_grid_tiles 1 1
pack_time 1 0.854886073
placed_wirelength_est 1 0.992415995
place_time 1 0.84763253
placed_CPD_est 1 1.019996764
min_chan_width
routed_wirelength 1 0.994228761
min_chan_width_route_time 1 0.817147572
crit_path_routed_wirelength
critical_path_delay
geomean_nonvirtual_intradomain_critical_path_delay
crit_path_route_time

comparison files are here :
figure8.xlsx
koios_medium.xlsx
multless_consts.xlsx
open_cores.xlsx
power_extended_arch_list.xlsx
strong_blocks_with_no_inputs.xlsx
strong_two_chains.xlsx
vtr_reg_qor_chain_depop.xlsx

@vaughnbetz
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This mostly looks OK, but there are a few missing or crazy numbers; are those run failures?

@amirarjmand93
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amirarjmand93 commented Jun 29, 2024

There are some QoR failures that I have attached here. After parsing the results using parse_vtr_task.py, I utilized the qor_compare.py script. However, this script encounters issues when trying to calculate the ratio sheets, as it leaves some metric values blank or with huge discrepancies. maybe it arises from column incompatibility between the Golden result and Parsing result sheets. the number of columns is unequal.
I used my own script to calculate the ratio and geomean.
Some metrics, such as "geomean_nonvirtual_intradomain_critical_path_delay," in koios_medium.xlsx have a value of -1 for entire rows in both the golden and parsing sheets.

image_2024-06-28_21-07-17

image_2024-06-28_21-44-41

image_2024-06-28_21-48-14

image_2024-06-28_21-50-21

image

@github-actions github-actions bot added the infra Project Infrastructure label Jul 8, 2024
@vaughnbetz
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I manually lined up some numbers from koios_medium, and they look OK (pre-packed blocks, post-packed blocks, post-packed nets, placement time, placement wirelength, placement cpd are all up or down slightly and fine).
It looks like the new results never ran the router (no meaningful numbers there) or didn't parse it into the excel sheet.

@vaughnbetz
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Since we have existing QoR data (@MohamedElgammal has it for the VTR 9 paper) I'll merge this, and @MohamedElgammal if you can generate new front end QoR for VTR and Koios we can use it as a double check, and for the VTR 9 paper.

@vaughnbetz vaughnbetz merged commit cb55d66 into master Jul 8, 2024
51 checks passed
@vaughnbetz vaughnbetz deleted the yosys_update branch July 8, 2024 20:55
@amirarjmand93
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@vaughnbetz have you seen my commit? I turned off two tests completely. vtr_reg_system_verilog and parmys_reg_strong.
but I think parmys_reg_strong should not be turned off completely and just the command cmake: "-DYOSYS_F4PGA_PLUGINS=ON " should be OFF. I was looking into it, but I noticed that you're merging it.

@vaughnbetz
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I suggest making a separate PR to turn the relevant tests back on then; getting them turned on ASAP would be a good idea as having CI tests turned off lets new bugs slip through.

Since there was no [WIP] in the title and no comment on pending testing for this I assumed it was ready to merge.

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