CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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Jul 19, 2024 - SystemVerilog
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RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 57 public repositories matching this topic...
VeeR EH1 core
fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer
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May 29, 2023 - SystemVerilog
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2
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Jan 7, 2025 - SystemVerilog
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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Jan 18, 2024 - SystemVerilog
Методические материалы по разработке процессора архитектуры RISC-V
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Dec 13, 2024 - SystemVerilog
Vector processor for RISC-V vector ISA
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Oct 19, 2020 - SystemVerilog
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
fpga riscv heterogeneous-parallel-programming shared-memory computer-architecture openmp-parallelization many-core-architectures heterogeneous-computing iommu openmp-offloading unified-virtual-memory
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Sep 18, 2023 - SystemVerilog
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
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Jan 7, 2025 - SystemVerilog
A Single Cycle Risc-V 32 bit CPU
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Feb 11, 2023 - SystemVerilog
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
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Dec 18, 2024 - SystemVerilog
DUTH RISC-V Superscalar Microprocessor
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Oct 23, 2024 - SystemVerilog
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
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Aug 28, 2023 - SystemVerilog
A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
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May 8, 2021 - SystemVerilog
RISCV CPU implementation in SystemVerilog
asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu
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Oct 8, 2024 - SystemVerilog
A Barrel design of RV32I
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Jul 30, 2023 - SystemVerilog