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replace null-cap CSR reset values with a tag clear (fixes issue 43) #101

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merged 4 commits into from
Feb 12, 2024
Merged

replace null-cap CSR reset values with a tag clear (fixes issue 43) #101

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69d5a5c
replace null-cap CSR reset values with a tag clear
tariqkurd-repo Feb 9, 2024
596c6d9
Merge branch 'riscv:main' into fix-issue-43
tariqkurd-repo Feb 12, 2024
7a5ee45
Update text to show correct CSR reset values
tariqkurd-repo Feb 12, 2024
0a0b442
correct mepcc, sepcc, sscratchc reset values
tariqkurd-repo Feb 12, 2024
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16 changes: 8 additions & 8 deletions src/csv/CHERI_CSR.csv
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Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
"Extended CSR","CLEN Address","Alias","XLEN Address","Mode","Permissions","Reset Value","Action on XLEN write","Action on CLEN write","Executable Vector","Data Pointer","Unseal On Execution","Store full metadata","Zcheri_legacy","Zcheri_purecap","Prerequisites","Description","","","","","","","","","","","","","","","","","","","","",""
"dpcc","0x7b9","dpc","0x7b1","D","DRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
"dpcc","0x7b9","dpc","0x7b1","D","DRW, <<asr_perm>>","tag=0, otherwise undefined","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","✔","","✔","✔","Sdext","Debug Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
"dscratch0c","0x7ba","dscratch0","0x7b2","D","DRW, <<asr_perm>>","<<infinite-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 0","","","","","","","","","","","","","","","","","","","","",""
"dscratch1c","0x7bb","dscratch1","0x7b3","D","DRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 1","","","","","","","","","","","","","","","","","","","","",""
"dscratch0c","0x7ba","dscratch0","0x7b2","D","DRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 0","","","","","","","","","","","","","","","","","","","","",""
"dscratch1c","0x7bb","dscratch1","0x7b3","D","DRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 1","","","","","","","","","","","","","","","","","","","","",""
"mtvecc","0x765","mtvec","0x305","M","MRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","✔","","","","✔","✔","M-mode","Machine Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
"mscratchc","0x760","mscratch","0x340","M","MRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","M-mode","Machine Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"mscratchc","0x760","mscratch","0x340","M","MRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","M-mode","Machine Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"mepcc","0x761","mepc","0x341","M","MRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","✔","","✔","✔","M-mode","Machine Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
Expand All @@ -18,16 +18,16 @@ Always update the CSR with <<CSETADDR>> even if the address didn't change, inclu
Vector range check ^*^ if vectored mode is programmed.","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","✔","","","","✔","✔","S-mode","Supervisor Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
"sscratchc","0x540","sscratch","0x140","S","SRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","S-mode","Supervisor Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"sscratchc","0x540","sscratch","0x140","S","SRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","S-mode","Supervisor Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"sepcc","0x541","sepc","0x141","S","SRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","✔","","✔","✔","S-mode","Supervisor Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
"jvtc","0x417","jvt","0x017","U","URW","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","","","✔","✔","Zcmt","Jump Vector Table Capability","","","","","","","","","","","","","","","","","","","","",""
"dddc","0x7bc","","","D","DRW, <<asr_perm>>","<<null-cap>>","","","","✔","","","✔","","Sdext","Debug Default Data Capabilty (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","",""
"mtdc","0x74c","","","M","MRW, <<asr_perm>>","<<null-cap>>","","","","","","","✔","","M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"stdc","0x163","","","S","SRW, <<asr_perm>>","<<null-cap>>","","","","","","","✔","","S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"dddc","0x7bc","","","D","DRW, <<asr_perm>>","tag=0, otherwise undefined","","","","✔","","","✔","","Sdext","Debug Default Data Capabilty (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","",""
"mtdc","0x74c","","","M","MRW, <<asr_perm>>","tag=0, otherwise undefined","","","","","","","✔","","M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"stdc","0x163","","","S","SRW, <<asr_perm>>","tag=0, otherwise undefined","","","","","","","✔","","S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"ddc","0x416","","","U","URW","<<infinite-cap>>","","","","✔","","","✔","","none","User Default Data Capability","","","","","","","","","","","","","","","","","","","","",""
"pcc","0xcb0","","","U","URO","<<infinite-cap>>
(address = boot address)","","","✔","","","","✔","✔","none","User Program Counter Capability (to allow reading in legacy mode)","","","","","","","","","","","","","","","","","","","","",""
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