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replace null-cap CSR reset values with a tag clear (fixes issue 43) #101

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merged 4 commits into from
Feb 12, 2024
Merged

replace null-cap CSR reset values with a tag clear (fixes issue 43) #101

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69d5a5c
replace null-cap CSR reset values with a tag clear
tariqkurd-repo Feb 9, 2024
596c6d9
Merge branch 'riscv:main' into fix-issue-43
tariqkurd-repo Feb 12, 2024
7a5ee45
Update text to show correct CSR reset values
tariqkurd-repo Feb 12, 2024
0a0b442
correct mepcc, sepcc, sscratchc reset values
tariqkurd-repo Feb 12, 2024
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16 changes: 8 additions & 8 deletions src/csv/CHERI_CSR.csv
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Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
"Extended CSR","CLEN Address","Alias","XLEN Address","Mode","Permissions","Reset Value","Action on XLEN write","Action on CLEN write","Executable Vector","Data Pointer","Unseal On Execution","Store full metadata","Zcheri_legacy","Zcheri_purecap","Prerequisites","Description","","","","","","","","","","","","","","","","","","","","",""
"dpcc","0x7b9","dpc","0x7b1","D","DRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
"dpcc","0x7b9","dpc","0x7b1","D","DRW, <<asr_perm>>","tag=0, otherwise undefined","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","✔","","✔","✔","Sdext","Debug Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
"dscratch0c","0x7ba","dscratch0","0x7b2","D","DRW, <<asr_perm>>","<<infinite-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 0","","","","","","","","","","","","","","","","","","","","",""
"dscratch1c","0x7bb","dscratch1","0x7b3","D","DRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 1","","","","","","","","","","","","","","","","","","","","",""
"dscratch0c","0x7ba","dscratch0","0x7b2","D","DRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 0","","","","","","","","","","","","","","","","","","","","",""
"dscratch1c","0x7bb","dscratch1","0x7b3","D","DRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","Sdext","Debug Scratch Capability 1","","","","","","","","","","","","","","","","","","","","",""
"mtvecc","0x765","mtvec","0x305","M","MRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","✔","","","","✔","✔","M-mode","Machine Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
"mscratchc","0x760","mscratch","0x340","M","MRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","M-mode","Machine Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"mscratchc","0x760","mscratch","0x340","M","MRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","M-mode","Machine Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"mepcc","0x761","mepc","0x341","M","MRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","✔","","✔","✔","M-mode","Machine Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
Expand All @@ -18,16 +18,16 @@ Always update the CSR with <<CSETADDR>> even if the address didn't change, inclu
Vector range check ^*^ if vectored mode is programmed.","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change, including the MODE field in the address for simplicity.
Vector range check ^*^ if vectored mode is programmed.","✔","","","","✔","✔","S-mode","Supervisor Trap-Vector Base-Address Capability","","","","","","","","","","","","","","","","","","","","",""
"sscratchc","0x540","sscratch","0x140","S","SRW, <<asr_perm>>","<<null-cap>>","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","S-mode","Supervisor Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"sscratchc","0x540","sscratch","0x140","S","SRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<CSETADDR>>.","direct write","","","","✔","✔","✔","S-mode","Supervisor Scratch Capability","","","","","","","","","","","","","","","","","","","","",""
"sepcc","0x541","sepc","0x141","S","SRW, <<asr_perm>>","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","✔","","✔","✔","S-mode","Supervisor Exception Program Counter Capability","","","","","","","","","","","","","","","","","","","","",""
"jvtc","0x417","jvt","0x017","U","URW","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
Always update the CSR with <<CSETADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
direct write if address didn't change","✔","","","","✔","✔","Zcmt","Jump Vector Table Capability","","","","","","","","","","","","","","","","","","","","",""
"dddc","0x7bc","","","D","DRW, <<asr_perm>>","<<null-cap>>","","","","✔","","","✔","","Sdext","Debug Default Data Capabilty (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","",""
"mtdc","0x74c","","","M","MRW, <<asr_perm>>","<<null-cap>>","","","","","","","✔","","M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"stdc","0x163","","","S","SRW, <<asr_perm>>","<<null-cap>>","","","","","","","✔","","S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"dddc","0x7bc","","","D","DRW, <<asr_perm>>","tag=0, otherwise undefined","","","","✔","","","✔","","Sdext","Debug Default Data Capabilty (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","",""
"mtdc","0x74c","","","M","MRW, <<asr_perm>>","tag=0, otherwise undefined","","","","","","","✔","","M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"stdc","0x163","","","S","SRW, <<asr_perm>>","tag=0, otherwise undefined","","","","","","","✔","","S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
"ddc","0x416","","","U","URW","<<infinite-cap>>","","","","✔","","","✔","","none","User Default Data Capability","","","","","","","","","","","","","","","","","","","","",""
"pcc","0xcb0","","","U","URO","<<infinite-cap>>
(address = boot address)","","","✔","","","","✔","✔","none","User Program Counter Capability (to allow reading in legacy mode)","","","","","","","","","","","","","","","","","","","","",""
14 changes: 9 additions & 5 deletions src/debug-integration.adoc
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Expand Up @@ -39,7 +39,9 @@ include::img/dpcreg.edn[]
==== Debug Program Counter Capability (dpcc)

The <<dpcc>> register is a extension to <<dpc>> that is able to hold a
capability. Its reset value is the <<null-cap>> capability.
capability.

{TAG_RESET_CSR}

.Debug program counter capability
include::img/dpccreg.edn[]
Expand Down Expand Up @@ -67,8 +69,9 @@ its mode, permissions, sealing or bounds.

The <<dscratch0>> register is as defined in cite:[riscv-debug-spec]. It is an
optional DXLEN-bit scratch register that can be used by implementations which
need it. Its reset value is the <<null-cap>> capability. <<dscratch0>> is
extended into <<dscratch0c>>.
need it. <<dscratch0>> is extended into <<dscratch0c>>.

{TAG_RESET_CSR}

.Debug scratch 0 register
include::img/dscratch0reg.edn[]
Expand All @@ -88,8 +91,9 @@ include::img/dscratch0creg.edn[]

The <<dscratch1>> register is as defined in cite:[riscv-debug-spec]. It is an
optional DXLEN-bit scratch register that can be used by implementations which
need it. Its reset value is the <<null-cap>> capability. <<dscratch1>> is
extended into <<dscratch1c>>.
need it. <<dscratch1>> is extended into <<dscratch1c>>.

{TAG_RESET_CSR}

.Debug scratch 0 register
include::img/dscratch1reg.edn[]
Expand Down
2 changes: 2 additions & 0 deletions src/riscv-cheri.adoc
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Expand Up @@ -62,6 +62,8 @@ endif::[]
:non-csrrw-or: <<CSRRWI>>, <<CSRRS>>, <<CSRRSI>>, <<CSRRC>> or <<CSRRCI>>
:non-csrrw-and: <<CSRRWI>>, <<CSRRS>>, <<CSRRSI>>, <<CSRRC>> and <<CSRRCI>>

:TAG_RESET_CSR: The tag of the CSR must be reset to zero. The reset values of the metadata and address fields are UNSPECIFIED.

///////////////////////////////////////////////////////////////////////////////
// Cap definitions
///////////////////////////////////////////////////////////////////////////////
Expand Down
12 changes: 8 additions & 4 deletions src/riscv-integration.adoc
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Expand Up @@ -545,7 +545,9 @@ include::img/mscratchreg.edn[]
==== Machine Scratch Register Capability (mscratchc)

The <<mscratchc>> register is an extension to <<mscratch>> that is able to hold
a capability. Its reset value is the <<null-cap>> capability.
a capability.

{TAG_RESET_CSR}
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It is not WARL, all capability fields must be implemented.

Expand All @@ -565,7 +567,7 @@ include::img/mepcreg.edn[]
==== Machine Exception Program Counter Capability (mepcc)

The <<mepcc>> register is an extension to <<mepc>> that is able to hold a
capability. Its reset value is the <<null-cap>> capability.
capability. Its reset value is the <<infinite-cap>> capability.

.Machine exception program counter capability register
include::img/mepccreg.edn[]
Expand Down Expand Up @@ -856,7 +858,9 @@ include::img/sscratchreg.edn[]
==== Supervisor Scratch Registers (sscratchc)

The <<sscratchc>> register is an extension to <<sscratch>> that is able to hold
a capability. Its reset value is the <<null-cap>> capability.
a capability.

{TAG_RESET_CSR}

It is not WARL, all capability fields must be implemented.

Expand All @@ -876,7 +880,7 @@ include::img/sepcreg.edn[]
==== Supervisor Exception Program Counter Capability (sepcc)

The <<sepcc>> register is an extension to <<sepc>> that is able to hold a
capability. Its reset value is the <<null-cap>> capability.
capability. Its reset value is the <<infinite-cap>> capability.

As shown in xref:CSR_exevectors[xrefstyle=short], <<sepcc>> is an executable
vector, so it need not be able to hold all possible invalid addresses.
Expand Down
15 changes: 10 additions & 5 deletions src/riscv-legacy-integration.adoc
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Expand Up @@ -226,10 +226,11 @@ shown in xref:legacy-csrnames-added[xrefstyle=short].
[#dddc,reftext="dddc"]
=== Debug Default Data Capability (dddc)

<<dddc>> is a register that is able to hold a capability. Its reset value is
the <<null-cap>> capability. The address is shown in
<<dddc>> is a register that is able to hold a capability. The address is shown in
xref:legacy-csrnames-added[xrefstyle=short].

{TAG_RESET_CSR}

.Debug default data capability
include::img/dddcreg.edn[]

Expand Down Expand Up @@ -327,7 +328,10 @@ hardware register (i.e. CLEN bits) to correctly decode capability bounds.

The <<mtdc>> register is capability width read/write register dedicated
for use by machine mode. Typically, it is used to hold a data capability to a
machine-mode hart-local context space, to load into <<ddc>>. <<mtdc>>'s reset
machine-mode hart-local context space, to load into <<ddc>>.

{TAG_RESET_CSR}

value is the <<null-cap>> capability.

.Machine-mode trap data capability register
Expand All @@ -352,8 +356,9 @@ CHERI execution mode is Capability. When CME=0, the mode is Legacy.

The <<stdc>> register is capability width read/write register dedicated
for use by supervisor mode. Typically, it is used to hold a data capability to
a supervisor-mode hart-local context space, to load into <<ddc>>. <<stdc>>'s
reset value is the <<null-cap>> capability.
a supervisor-mode hart-local context space, to load into <<ddc>>.

{TAG_RESET_CSR}

.Supervisor trap data capability register (*stdc*)
include::img/stdcreg.edn[]
Expand Down
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