Update the memory alignment within the Cortex-R5 port asm code #1023
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Update alignment in ARM_CR5 port. This is the same patch as 553caa1 provided by Richard Barry for issue FreeRTOS#426 (ARM_CA9). Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
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Thanks for the PR, I am sending to the team for code review. |
Skptak
approved these changes
Apr 9, 2024
Did you face any problem or are you making these changes in anticipation of a problem? |
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This patch improves memory alignment for storing the floating point registers when switching best regards, Florian La Roche |
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Thank you for explanation. |
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aggarg
approved these changes
Apr 9, 2024
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Update alignment in ARM_CR5 port.
This is the same patch as 553caa1 provided by Richard Barry for issue #426 (ARM_CA9).
Description
ARM_CA9 and ARM_CR5 are very close. This patch was applied to ARM_CA9, so it
might also make sense to apply it to ARM_CR5.
Test Steps
This was just observed by looking at the changes between A9 and R5, no real
testing was conducted.
Checklist:
Related Issue
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