Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Update the memory alignment within the Cortex-A9 port asm code #426

Merged
merged 20 commits into from
Dec 9, 2023

Conversation

RichardBarry
Copy link
Contributor

Description

Update the assembly code used in the Cortex-A9 port to ensure stack alignment before calling vTaskSwitchContext() in case user code added to the function (maybe via a trace macro or other mechanism) requires the more strict alignment. That would be the case if, as an example, floating point instructions were used.

Test Steps

The self monitoring integration tests have been running for several weeks with no issues.

By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

@RichardBarry RichardBarry requested a review from a team as a code owner December 19, 2021 17:43
@codecov
Copy link

codecov bot commented Dec 19, 2021

Codecov Report

All modified and coverable lines are covered by tests ✅

Comparison is base (a79752a) 93.78% compared to head (32462fd) 93.78%.

Additional details and impacted files
@@           Coverage Diff           @@
##             main     #426   +/-   ##
=======================================
  Coverage   93.78%   93.78%           
=======================================
  Files           6        6           
  Lines        3184     3184           
  Branches      885      885           
=======================================
  Hits         2986     2986           
  Misses         91       91           
  Partials      107      107           
Flag Coverage Δ
unittests 93.78% <ø> (ø)

Flags with carried forward coverage won't be shown. Click here to find out more.

☔ View full report in Codecov by Sentry.
📢 Have feedback on the report? Share it here.

aggarg
aggarg previously approved these changes Dec 20, 2021
@Mancent Mancent linked an issue May 21, 2023 that may be closed by this pull request
Copy link
Member

@chinglee-iot chinglee-iot left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Re-verify the ARM_CA9 port on zynq board without problem.

@sonarqubecloud
Copy link

Kudos, SonarCloud Quality Gate passed!    Quality Gate passed

Bug A 0 Bugs
Vulnerability A 0 Vulnerabilities
Security Hotspot A 0 Security Hotspots
Code Smell A 0 Code Smells

No Coverage information No Coverage information
0.8% 0.8% Duplication

Copy link

sonarqubecloud bot commented Dec 8, 2023

Kudos, SonarCloud Quality Gate passed!    Quality Gate passed

Bug A 0 Bugs
Vulnerability A 0 Vulnerabilities
Security Hotspot A 0 Security Hotspots
Code Smell A 0 Code Smells

No Coverage information No Coverage information
0.8% 0.8% Duplication

@aggarg aggarg merged commit 553caa1 into FreeRTOS:main Dec 9, 2023
17 checks passed
laroche added a commit to laroche/FreeRTOS-Kernel that referenced this pull request Apr 7, 2024
Update alignment in ARM_CR5 port.

This is the same patch as 553caa1
provided by Richard Barry for issue FreeRTOS#426 (ARM_CA9).

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
aggarg pushed a commit that referenced this pull request Apr 9, 2024
Update alignment in ARM_CR5 port.

This is the same patch as 553caa1
provided by Richard Barry for issue #426 (ARM_CA9).

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

> - [ ] ```
6 participants