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Add MCXN947 sai module support #77534

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merged 5 commits into from
Jan 17, 2025
Merged

Add MCXN947 sai module support #77534

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9c8fa33
clock: driver/clock_control: Add sai clock support for syscon.
mcuxted May 31, 2024
55ffc95
drivers: drivers/i2s: fix sai issue for support frdm_mcxn497
mcuxted May 31, 2024
aebbd9f
dts: arm/nxp/mcxn94x: Add sai nodes for NXP mcxn94x
mcuxted May 31, 2024
a2a3d70
boards: nxp/frdm_mcxn947: Support sai for NXP frdm_mcxn947
mcuxted May 31, 2024
a959efd
samples: drivers/i2s: Support i2s example for NXP frdm_mcxn947
mcuxted May 31, 2024
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37 changes: 23 additions & 14 deletions boards/nxp/frdm_mcxn947/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -131,21 +131,18 @@ static int frdm_mcxn947_init(void)

CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
/* Set up PLL1 for 80 MHz FlexCAN clock */
const pll_setup_t pll1Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) |
SCG_SPLLCTRL_SELP(13U),
.pllndiv = SCG_SPLLNDIV_NDIV(3U),
.pllpdiv = SCG_SPLLPDIV_PDIV(1U),
.pllmdiv = SCG_SPLLMDIV_MDIV(10U),
.pllRate = 80000000U
};
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
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Is the FlexCAN clock setup deleted?

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The clock source of flexcan has been switched to kFRO_HF_to_FLEXCAN0

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However I don't see flexcan in this list?

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The original clk source of flexcan is pll1. Due to the conflict with sai mclk clock source, the clock source of flexcan is switched from kPLL1_CLK0_to_FLEXCAN0 to kFRO_HF_to_FLEXCAN0 to ensure the use of flexcan(CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0);).

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@mcuxted , can you please look at this code?

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@hakehuang , can we confirm that this change does not break Flexcan support on this board.

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@hakehuang hakehuang Jan 16, 2025 •
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@mmahadevan108 good point. looks OK for all timings

2025-01-16 19:18:10,194 - twister - DEBUG - DEVICE: *** Booting Zephyr OS build v4.0.0-2200-g227d86b63ed2 ***
2025-01-16 19:18:10,197 - twister - DEBUG - DEVICE: Running TESTSUITE can_timing
2025-01-16 19:18:10,203 - twister - DEBUG - DEVICE: ===================================================================
2025-01-16 19:18:10,207 - twister - DEBUG - DEVICE: testing on device can@d4000 @ 48000000 Hz
2025-01-16 19:18:10,208 - twister - DEBUG - DEVICE: START - test_timing
2025-01-16 19:18:10,221 - twister - DEBUG - DEVICE: testing bitrate 10000, sample point 87.5%: sjw = 1, prop_seg = 8, phase_seg1 = 8, phase_seg2 = 3, prescaler = 240 OK, sample point error 2.5%
2025-01-16 19:18:10,233 - twister - DEBUG - DEVICE: testing bitrate 20000, sample point 87.5%: sjw = 1, prop_seg = 6, phase_seg1 = 7, phase_seg2 = 2, prescaler = 150 OK, sample point error 0.0%
2025-01-16 19:18:10,245 - twister - DEBUG - DEVICE: testing bitrate 50000, sample point 87.5%: sjw = 1, prop_seg = 6, phase_seg1 = 7, phase_seg2 = 2, prescaler = 60 OK, sample point error 0.0%
2025-01-16 19:18:10,258 - twister - DEBUG - DEVICE: testing bitrate 125000, sample point 87.5%: sjw = 1, prop_seg = 6, phase_seg1 = 7, phase_seg2 = 2, prescaler = 24 OK, sample point error 0.0%
2025-01-16 19:18:10,269 - twister - DEBUG - -- west flash: using runner jlink
2025-01-16 19:18:10,269 - twister - DEBUG - DEVICE: testing bitrate 250000, sample point 87.5%: sjw = 1, prop_seg = 6, phase_seg1 = 7, phase_seg2 = 2, prescaler = 12 OK, sample point error 0.0%
2025-01-16 19:18:10,282 - twister - DEBUG - DEVICE: testing bitrate 500000, sample point 87.5%: sjw = 1, prop_seg = 6, phase_seg1 = 7, phase_seg2 = 2, prescaler = 6 OK, sample point error 0.0%
2025-01-16 19:18:10,295 - twister - DEBUG - DEVICE: testing bitrate 800000, sample point 80.0%: sjw = 2, prop_seg = 7, phase_seg1 = 8, phase_seg2 = 4, prescaler = 3 OK, sample point error 0.0%
2025-01-16 19:18:10,307 - twister - DEBUG - DEVICE: testing bitrate 1000000, sample point 75.0%: sjw = 2, prop_seg = 5, phase_seg1 = 6, phase_seg2 = 4, prescaler = 3 OK, sample point error 0.0%
2025-01-16 19:18:10,310 - twister - DEBUG - DEVICE: PASS - test_timing in 0.100 seconds
2025-01-16 19:18:10,316 - twister - DEBUG - DEVICE: ===================================================================
2025-01-16 19:18:10,319 - twister - DEBUG - DEVICE: START - test_timing_data
2025-01-16 19:18:10,322 - twister - DEBUG - DEVICE: SKIP - test_timing_data in 0.001 seconds
2025-01-16 19:18:10,328 - twister - DEBUG - DEVICE: ===================================================================
2025-01-16 19:18:10,331 - twister - DEBUG - DEVICE: TESTSUITE can_timing succeeded
2025-01-16 19:18:10,335 - twister - DEBUG - DEVICE: ------ TESTSUITE SUMMARY START ------
2025-01-16 19:18:10,343 - twister - DEBUG - DEVICE: SUITE PASS - 100.00% [can_timing]: pass = 1, fail = 0, skip = 1, total = 2 duration = 0.101 seconds
2025-01-16 19:18:10,348 - twister - DEBUG - DEVICE: - PASS - [can_timing.test_timing] duration = 0.100 seconds
2025-01-16 19:18:10,354 - twister - DEBUG - DEVICE: - SKIP - [can_timing.test_timing_data] duration = 0.001 seconds
2025-01-16 19:18:10,357 - twister - DEBUG - DEVICE: ------ TESTSUITE SUMMARY END ------
2025-01-16 19:18:10,364 - twister - DEBUG - DEVICE: ===================================================================
2025-01-16 19:18:10,367 - twister - DEBUG - DEVICE: RunID: e34ce6648f488d5bfb13441d421780dd
2025-01-16 19:18:10,370 - twister - DEBUG - DEVICE: PROJECT EXECUTION SUCCESSFUL

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Thanks @hakehuang . Can you please approve this PR if it looks good to you per your testing.

/* < Set up PLL1 */
const pll_setup_t pll1_Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
SCG_SPLLCTRL_SELP(1U),
.pllndiv = SCG_SPLLNDIV_NDIV(25U),
.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
.pllRate = 24576000U};

/* Configure PLL1 to the desired values */
CLOCK_SetPLL1Freq(&pll1Setup);
/* PLL1 Monitor is disabled */
CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);
CLOCK_SetPLL1Freq(&pll1_Setup);
/* Set PLL1 CLK0 divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
#endif
Expand Down Expand Up @@ -250,7 +247,7 @@ static int frdm_mcxn947_init(void)

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U);
CLOCK_AttachClk(kPLL1_CLK0_to_FLEXCAN0);
CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0);
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#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0))
Expand Down Expand Up @@ -383,6 +380,18 @@ static int frdm_mcxn947_init(void)
CLOCK_AttachClk(kFRO_HF_to_SCT);
#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0))
CLOCK_SetClkDiv(kCLOCK_DivSai0Clk, 1u);
CLOCK_AttachClk(kPLL1_CLK0_to_SAI0);
CLOCK_EnableClock(kCLOCK_Sai0);
#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
CLOCK_SetClkDiv(kCLOCK_DivSai1Clk, 1u);
CLOCK_AttachClk(kPLL1_CLK0_to_SAI1);
CLOCK_EnableClock(kCLOCK_Sai1);
#endif

/* Set SystemCoreClock variable. */
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;

Expand Down
2 changes: 2 additions & 0 deletions boards/nxp/frdm_mcxn947/doc/index.rst
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Expand Up @@ -97,6 +97,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| FLEXIO | on-chip | flexio |
+-----------+------------+-------------------------------------+
| SAI | on-chip | i2s |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | flexio; MIPI-DBI. Tested with |
| | | :ref:`lcd_par_s035` |
+-----------+------------+-------------------------------------+
Expand Down
25 changes: 25 additions & 0 deletions boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi
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Expand Up @@ -92,6 +92,31 @@
};
};

pinmux_sai1: pinmux_sai1 {
group0 {
pinmux = <SAI1_TX_BCLK_PIO3_16>,
<SAI1_TX_FS_PIO3_17>,
<SAI1_TXD0_PIO3_20>,
<SAI1_RX_FS_PIO3_19>,
<SAI1_RX_BCLK_PIO3_18>,
<SAI1_RXD0_PIO3_21>;
drive-strength = "high";
slew-rate = "fast";
input-enable;
};
};

pinmux_sai0: pinmux_sai0 {
group0 {
pinmux = <SAI0_TXD0_PIO2_2>,
<SAI0_TX_BCLK_PIO2_6>,
<SAI0_TX_FS_PIO2_7>;
drive-strength = "high";
slew-rate = "fast";
input-enable;
};
};

pinmux_enet_qos: pinmux_enet_qos {
mdio_group {
pinmux = <ENET0_MDC_PIO1_20>,
Expand Down
10 changes: 10 additions & 0 deletions boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi
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Expand Up @@ -206,6 +206,16 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
pinctrl-names = "default";
};

&sai1 {
pinctrl-0 = <&pinmux_sai1>;
pinctrl-names = "default";
};

&sai0 {
pinctrl-0 = <&pinmux_sai0>;
pinctrl-names = "default";
};

&enet {
pinctrl-0 = <&pinmux_enet_qos>;
pinctrl-names = "default";
Expand Down
7 changes: 7 additions & 0 deletions boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi
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Expand Up @@ -233,3 +233,10 @@ zephyr_udc0: &usb1 {
&sc_timer {
status = "okay";
};

&sai1 {
status = "okay";
};
&sai0 {
status = "okay";
};
1 change: 1 addition & 0 deletions boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
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Expand Up @@ -23,6 +23,7 @@ supported:
- flash
- gpio
- i2c
- i2s
- i3c
- pwm
- regulator
Expand Down
15 changes: 15 additions & 0 deletions drivers/clock_control/clock_control_mcux_syscon.c
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Expand Up @@ -412,6 +412,21 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
#endif
#endif /* CONFIG_MEMC_MCUX_FLEXSPI */

#if defined(CONFIG_I2S_MCUX_SAI)
case MCUX_SAI0_CLK:
#if (FSL_FEATURE_SOC_I2S_COUNT == 1)
*rate = CLOCK_GetSaiClkFreq();
#else
*rate = CLOCK_GetSaiClkFreq(0);
#endif
break;
#if (FSL_FEATURE_SOC_I2S_COUNT == 2)
case MCUX_SAI1_CLK:
*rate = CLOCK_GetSaiClkFreq(1);
break;
#endif
#endif /* CONFIG_I2S_MCUX_SAI */

#ifdef CONFIG_ETH_NXP_ENET_QOS
case MCUX_ENET_QOS_CLK:
*rate = CLOCK_GetFreq(kCLOCK_BusClk);
Expand Down
6 changes: 5 additions & 1 deletion drivers/i2s/Kconfig.mcux
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@@ -1,6 +1,6 @@
# MCUX I2S driver configuration options

# Copyright (c) 2021, NXP
# Copyright 2021,2024 NXP
# SPDX-License-Identifier: Apache-2.0

menuconfig I2S_MCUX_SAI
Expand Down Expand Up @@ -28,4 +28,8 @@ config I2S_EDMA_BURST_SIZE
help
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I2S EDMA burst size in bytes.

config I2S_HAS_PLL_SETTING
bool "I2S will setting pll in driver"
default y

endif # I2S_MCUX_SAI
29 changes: 16 additions & 13 deletions drivers/i2s/i2s_mcux_sai.c
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ struct i2s_mcux_config {
uint32_t pll_pd;
uint32_t pll_num;
uint32_t pll_den;
uint32_t *mclk_control_base;
uint32_t mclk_control_base;
uint32_t mclk_pin_mask;
uint32_t mclk_pin_offset;
uint32_t tx_channel;
Expand Down Expand Up @@ -400,9 +400,10 @@ static void i2s_dma_rx_callback(const struct device *dma_dev, void *arg, uint32_
static void enable_mclk_direction(const struct device *dev, bool dir)
{
const struct i2s_mcux_config *dev_cfg = dev->config;
uint32_t control_base = dev_cfg->mclk_control_base;
uint32_t offset = dev_cfg->mclk_pin_offset;
uint32_t mask = dev_cfg->mclk_pin_mask;
uint32_t *base = (uint32_t *)(dev_cfg->mclk_control_base + offset);
uint32_t *base = (uint32_t *)(control_base + offset);

if (dir) {
*base |= mask;
Expand Down Expand Up @@ -1030,6 +1031,7 @@ static void i2s_mcux_isr(void *arg)

static void audio_clock_settings(const struct device *dev)
{
#ifdef CONFIG_I2S_HAS_PLL_SETTING
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@mmahadevan108 mmahadevan108 Jan 8, 2025 •
edited
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Instead of adding a Kconfig, ideally we should move this code out of the driver and into the soc.c file. This may not be required as part of this PR. If you can do it then that would be great.

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I also agree that the PLL configuration should be moved out of the i2s driver and configured using other methods，This may also cause the pll configuration to be overwritten.
In MCXN9, we can use the SDK to configure the PLL in the board.h. Is it a way to control the PLL outside the driver on other devices?

clock_audio_pll_config_t audioPllConfig;
const struct i2s_mcux_config *dev_cfg = dev->config;
uint32_t clock_name = (uint32_t)dev_cfg->clk_sub_sys;
Expand All @@ -1055,6 +1057,7 @@ static void audio_clock_settings(const struct device *dev)
#endif /* CONFIG_SOC_SERIES */

CLOCK_InitAudioPll(&audioPllConfig);
#endif
}

static int i2s_mcux_initialize(const struct device *dev)
Expand Down Expand Up @@ -1113,7 +1116,8 @@ static int i2s_mcux_initialize(const struct device *dev)
/* master clock configurations */
#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \
(defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV)))
mclkConfig.mclkHz = mclk;
mclkConfig.mclkSourceClkHz = mclk;
#endif
Expand All @@ -1140,16 +1144,15 @@ static DEVICE_API(i2s, i2s_mcux_driver_api) = {
\
static const struct i2s_mcux_config i2s_##i2s_id##_config = { \
.base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id), \
.clk_src = DT_INST_PROP(i2s_id, clock_mux), \
.clk_pre_div = DT_INST_PROP(i2s_id, pre_div), \
.clk_src_div = DT_INST_PROP(i2s_id, podf), \
.pll_src = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, src, value), \
.pll_lp = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, lp, value), \
.pll_pd = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, pd, value), \
.pll_num = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, num, value), \
.pll_den = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, den, value), \
.mclk_control_base = \
(uint32_t *)DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(i2s_id), pinmuxes)), \
.clk_src = DT_INST_PROP_OR(i2s_id, clock_mux, 0), \
.clk_pre_div = DT_INST_PROP_OR(i2s_id, pre_div, 0), \
.clk_src_div = DT_INST_PROP_OR(i2s_id, podf, 0), \
.pll_src = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, src, value, 0), \
.pll_lp = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, lp, value, 0), \
.pll_pd = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, pd, value, 0), \
.pll_num = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, num, value, 0), \
.pll_den = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, den, value, 0), \
.mclk_control_base = DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(i2s_id), pinmuxes)), \
.mclk_pin_mask = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, function), \
.mclk_pin_offset = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, pin), \
.clk_sub_sys = \
Expand Down
33 changes: 33 additions & 0 deletions dts/arm/nxp/nxp_mcxn94x_common.dtsi
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Expand Up @@ -1040,6 +1040,39 @@
clock-src = <0>;
alarms-count = <1>;
};

sai0: sai@106000 {
compatible = "nxp,mcux-i2s";
#address-cells = <1>;
#size-cells = <0>;
#pinmux-cells = <2>;
reg = < 0x106000 0x1000>;
clocks = <&syscon MCUX_SAI0_CLK>;
pinmuxes = <&sai0 0x100 0x40000000>;
interrupts = <59 0>;
dmas = <&edma0 0 99>, <&edma0 0 100>;
dma-names = "rx", "tx";
nxp,tx-channel = <1>;
nxp,tx-dma-channel = <0>;
nxp,rx-dma-channel = <1>;
status = "disabled";
};
sai1: sai@107000 {
compatible = "nxp,mcux-i2s";
#address-cells = <1>;
#size-cells = <0>;
#pinmux-cells = <2>;
reg = < 0x107000 0x1000>;
clocks = <&syscon MCUX_SAI1_CLK>;
pinmuxes = <&sai1 0x100 0x40000000>;
interrupts = <60 0>;
dmas = <&edma0 0 101>, <&edma0 0 102>;
dma-names = "rx", "tx";
nxp,tx-channel = <1>;
nxp,tx-dma-channel = <2>;
nxp,rx-dma-channel = <3>;
status = "disabled";
};
};

&systick {
Expand Down
7 changes: 5 additions & 2 deletions dts/bindings/i2s/nxp,mcux-i2s.yaml
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@@ -1,4 +1,4 @@
# Copyright 2021,2023 NXP
# Copyright 2021,2023-2024 NXP
# SPDX-License-Identifier: Apache-2.0

description: NXP mcux SAI-I2S controller
Expand Down Expand Up @@ -62,6 +62,9 @@ properties:
description: tx channel the maximum number is SOC dependent

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clock-mux:
required: true
type: int
description: Clock mux source for SAI root clock

pinmux-cells:
- pin
- function
3 changes: 3 additions & 0 deletions include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
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Expand Up @@ -115,4 +115,7 @@
#define MCUX_XSPI1_CLK MCUX_LPC_CLK_ID(0x15, 0x01)
#define MCUX_XSPI2_CLK MCUX_LPC_CLK_ID(0x15, 0x02)

#define MCUX_SAI0_CLK MCUX_LPC_CLK_ID(0x16, 0x00)
#define MCUX_SAI1_CLK MCUX_LPC_CLK_ID(0x16, 0x01)

#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */
5 changes: 5 additions & 0 deletions soc/nxp/mcx/mcxn/Kconfig.defconfig
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Expand Up @@ -27,4 +27,9 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config FLASH_FILL_BUFFER_SIZE
default 128

# The existing SAI diver cannot initialize the PLL on the board,
# so the PLL settings will not be performed in the driver.
config I2S_HAS_PLL_SETTING
default n

endif # SOC_SERIES_MCXN
2 changes: 2 additions & 0 deletions tests/drivers/i2s/i2s_api/testcase.yaml
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Expand Up @@ -6,6 +6,7 @@ tests:
- userspace
filter: not CONFIG_I2S_TEST_USE_GPIO_LOOPBACK
platform_exclude:
- frdm_mcxn947/mcxn947/cpu0
- mimxrt595_evk/mimxrt595s/cm33
- mimxrt685_evk/mimxrt685s/cm33
drivers.i2s.gpio_loopback:
Expand All @@ -18,6 +19,7 @@ tests:
filter: CONFIG_I2S_TEST_USE_GPIO_LOOPBACK
harness: ztest
platform_exclude:
- frdm_mcxn947/mcxn947/cpu0
- mimxrt595_evk/mimxrt595s/cm33
- mimxrt685_evk/mimxrt685s/cm33
harness_config:
Expand Down
7 changes: 7 additions & 0 deletions tests/drivers/i2s/i2s_speed/Readme.txt
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Expand Up @@ -10,3 +10,10 @@ signals externally on the EVK. These are the HW changes required to run this te
- Short BCLK J9-pin1 (SAI1_RX_BCLK) to J66-pin1 (SAI4_TX_BCLK)
- Short SYNC J9-pin5 (SAI1_RX_SYNC) to J64-pin1 (SAI4_TX_SYNC)
- Short Data J61-pin1 (SAI1_RX_DATA) to J63-pin1 (SAI4_TX_DATA)

FRDM-MCXN947:
This board uses CONFIG_I2S_TEST_SEPARATE_DEVICES=y and connects two SAI peripherals by shorting
signals externally on the EVK. These are the HW changes required to run this test:
- Short BCLK J1-pin9 (SAI1_RX_BCLK/P3_18) to J3-pin15 (SAI0_TX_BCLK/P2_6)
- Short SYNC J1-pin13 (SAI1_RX_FS/P3_19) to J3-pin13 (SAI0_TX_FS/P2_7)
- Short Data J1-pin15 (SAI1_RXD0/P3_21) to J3-pin7 (SAI0_TXD0/P2_2)
25 changes: 25 additions & 0 deletions tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.conf
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#
# Copyright (c) 2024, NXP
#
# SPDX-License-Identifier: Apache-2.0
#

# SAI peripheral does not have loopback mode. Use 2 SAI peripherals connected
# together externally.
CONFIG_I2S_TEST_SEPARATE_DEVICES=y

# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs)
# together, and should be sized as needed by the application. If not large
# enough, the DMA may starve. Symptoms of this issue include transmit blocks
# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3.
CONFIG_DMA_TCD_QUEUE_SIZE=4

# Repeat test continually to help find intermittent issues
CONFIG_ZTEST_RETEST_IF_PASSED=y

# I2S and DMA logging can occur in interrupt context, and interfere with I2S
# stream timing. If using either logging, set logging to deferred
# CONFIG_LOG_MODE_DEFERRED=y

CONFIG_DMA_LOG_LEVEL_OFF=y
CONFIG_I2S_LOG_LEVEL_OFF=y
11 changes: 11 additions & 0 deletions tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.overlay
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/* i2s_speed with CONFIG_I2S_TEST_SEPARATE_DEVICES=y uses two I2S peripherals:
* i2s-node0 is the receiver
* i2s-node1 is the transmitter
*/

/ {
aliases {
i2s-node0 = &sai1;
i2s-node1 = &sai0;
};
};
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