drivers: dma: stm32: bdma support for H7

[heinwessels]

Implement STM32H7 BDMA driver and integrate into dmamux

Co-authored-by: Jeroen van Dooren jeroen.van.dooren@nobleo.nl
Signed-off-by: Hein Wessels heinwessels93@gmail.com

[heinwessels]

This functionality is currently being verified using samples/drivers/adc in combination with #52965, with the following additional changes:

samples/drivers/adc/src/main.c

__in_section(shared_sram4, adc3,
	     dma_ds) static int16_t buffer[ARRAY_SIZE(adc_channels)] __aligned(32);

samples/drivers/adc/nucleo_h743zi.overlay

#include <zephyr/dt-bindings/adc/adc.h>

/ {
	zephyr,user {
		/*
		 * Note: Data in ADC results buffer will not be in the order
		 * that they are defined here, but as channels selection is done
		 * by a bitmask, they will be sorted instead in a way that
		 * lowest channel number result is on lowest buffer address
		 */
		io-channels = <&adc3 1>, <&adc3 2>;
	};
};

&adc3 {
	dmas = < &dmamux2 0 17 0x2C80>;
	dma-names = "dmamux";

	#address-cells = <1>;
	#size-cells = <0>;

	channel@1 {
		reg = <1>;
		zephyr,gain = "ADC_GAIN_1";
		zephyr,reference = "ADC_REF_INTERNAL";
		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
		zephyr,resolution = <12>;
	};

	channel@2 {
		reg = <2>;
		zephyr,gain = "ADC_GAIN_1";
		zephyr,reference = "ADC_REF_INTERNAL";
		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
		zephyr,resolution = <12>;
	};
};

&bdma1 {
	status="okay";
};

&dmamux2 {
	status="okay";
};

[FRASTM]

Do you also have tests/drivers/dma/loop_transfer and tests/drivers/dma/chan_blen_transfer PASSED with bdma on any stm32h7 board ?

[heinwessels]

Do you also have tests/drivers/dma/loop_transfer and tests/drivers/dma/chan_blen_transfer PASSED with bdma on any stm32h7 board ?

@FRASTM not yet, wasn't sure about them. I will add tests to a seperate commit in this PR as well. Thanks!

[heinwessels]

Do you also have tests/drivers/dma/loop_transfer and tests/drivers/dma/chan_blen_transfer PASSED with bdma on any stm32h7 board ?

Tested, and both tests run successfully. However, both already have an DMA test for the nucleo_h743zi for dmamux1, which means I can't add another test for dmamux2. The test only supports one dma. I'm happy to expand the testing to support multiple dma's if I can pack it into this PR (with specific commits of course).

[hakehuang]

all DMA regression tested on NXP FRDM_K64F platfrom. no issues found

[erwango]

Some last comments.
Also, my request about splitting commits impacting dmamux still stands

[FRASTM]

When adding the section for the SRAM4 to map BDMA buffers, are the clock and power already present to supply the D3 domain ?

[heinwessels]

Not sure what you mean? Adding this linker section will not change the order in SRAM sections or this driver is initialized. And the first time the BDMA knows about SRAM4 is during INIT_LEVEL_APPLICATION, and by then everything is obviously started up as expected.