dts: include: arm: st: usb: Add USB PHY clock rate support for STM32U…

…5xxx

The existing code assumes that the HSE clock is a 16MHz crystal, however
the hardware allows for a list of possible HSE clock values.

Add them here as an enum, configure it for the STM32U595 chipset
(which is the only device I have access to for testing).

This addresses Issue #79825 .

* Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the
  stm32u5 CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
* Add a list of possible values to use in the DT bindings directory
* Add a new PHY (st,stm32-otghs-phy) with an enum list matching the
  above list
* Add support in the USB driver for checking the clock-cfg entry
  and compiling in the correct clock rate.
* And also handle an out of enum configuration by failing compilation.

Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>

drivers/usb/device/usb_dc_stm32.c

@@ -23,6 +23,7 @@
 #include <zephyr/usb/usb_device.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/dt-bindings/phy/stm32u5_otg_hs_phy.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/pinctrl.h>
 #include "stm32_hsem.h"
@@ -36,6 +37,21 @@ LOG_MODULE_REGISTER(usb_dc_stm32);
 #error "Only one interface should be enabled at a time, OTG FS or OTG HS"
 #endif
 
+/*
+ * Some STM32U5xx parts support a USB HS PHY which is clocked by the HSE clock or PLL1_P
+ * clock directly.  This requires specific configuration.
+ */
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy)
+#if DT_NODE_HAS_PROP(DT_PHANDLE_BY_IDX(DT_NODELABEL(usbotg_hs), phys, 0), clock_cfg)
+#define OTG_HS_PHY_REFERENCE_CLOCK                                                                 \
+	_CONCAT(SYSCFG_OTG_HS_PHY_CLK_SELECT_,                                                     \
+		DT_PROP(DT_PHANDLE(DT_NODELABEL(usbotg_hs), phys), clock_cfg))
+#else
+#define OTG_HS_PHY_REFERENCE_CLOCK SYSCFG_OTG_HS_PHY_CLK_SELECT_1
+#endif
+
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy) */
+
 /*
  * Vbus sensing is determined based on the presence of the hardware detection
  * pin(s) in the device tree. E.g: pinctrl-0 = <&usb_otg_fs_vbus_pa9 ...>;
@@ -217,7 +233,7 @@ static int usb_dc_stm32_clock_enable(void)
 		return -ENODEV;
 	}
 
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) && defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy)
 	/* Sequence to enable the power of the OTG HS on a stm32U5 serie : Enable VDDUSB */
 	bool pwr_clk = LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PWR);
 
@@ -246,7 +262,7 @@ static int usb_dc_stm32_clock_enable(void)
 
 	/* Set the OTG PHY reference clock selection (through SYSCFG) block */
 	LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SYSCFG);
-	HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1);
+	HAL_SYSCFG_SetOTGPHYReferenceClockSelection(OTG_HS_PHY_REFERENCE_CLOCK);
 	/* Configuring the SYSCFG registers OTG_HS PHY : OTG_HS PHY enable*/
 	HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
 #elif defined(PWR_USBSCR_USB33SV) || defined(PWR_SVMCR_USV)
@@ -333,7 +349,7 @@ static int usb_dc_stm32_clock_disable(void)
 		LOG_ERR("Unable to disable USB clock");
 		return -EIO;
 	}
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) && defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy)
 	LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_USBPHY);
 #endif
 

dts/arm/st/u5/stm32u5.dtsi

@@ -20,6 +20,7 @@
 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
 #include <zephyr/dt-bindings/adc/stm32u5_adc.h>
 #include <zephyr/dt-bindings/power/stm32_pwr.h>
+#include <zephyr/dt-bindings/phy/stm32u5_otg_hs_phy.h>
 #include <freq.h>
 
 / {

dts/arm/st/u5/stm32u595.dtsi

@@ -107,15 +107,15 @@
 			ram-size = <4096>;
 			maximum-speed = "high-speed";
 			clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
-				 <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
+				 <&rcc STM32_SRC_HSI48 OTGHS_SEL(0)>;
 			phys = <&otghs_phy>;
 			status = "disabled";
 		};
 	};
 
 	otghs_phy: otghs_phy {
-		/* Clock source defined by USBPHYC_SEL in */
-		compatible = "usb-nop-xceiv";
+		/* Clock source defined by OTGHS_SEL() in usbotg_hs `clocks` */
+		compatible = "st,stm32u5-otghs-phy";
 		#phy-cells = <0>;
 	};
 

dts/bindings/phy/st,stm32u5-otghs-phy.yaml

@@ -0,0 +1,26 @@
+# Copyright (c) 2024 Meta
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    This binding is to be used by the STM32U5xx transceivers which are built-in
+    with USB HS PHY IP and a configurable HSE clock source.
+
+compatible: "st,stm32u5-otghs-phy"
+
+include: phy-controller.yaml
+
+properties:
+  "#phy-cells":
+    const: 0
+
+  clock-cfg:
+    type: int
+    enum:
+      - 1 # OTGHS_PHY_CLK_16MHZ
+      - 2 # OTGHS_PHY_CLK_19P2MHZ
+      - 3 # OTGHS_PHY_CLK_20MHZ
+      - 4 # OTGHS_PHY_CLK_24MHZ
+      - 5 # OTGHS_PHY_CLK_26MHZ
+      - 6 # OTGHS_PHY_CLK_32MHZ
+    description: |
+      The clock source speed configuration for this PHY.

include/zephyr/dt-bindings/clock/stm32u5_clock.h

@@ -122,7 +122,7 @@
 #define HSPI_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR2_REG)
 #define I2C5_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR2_REG)
 #define I2C6_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR2_REG)
-#define USBPHYC_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG)
+#define OTGHS_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG)
 /** CCIPR3 devices */
 #define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG)
 #define SPI3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG)

include/zephyr/dt-bindings/phy/stm32u5_otg_hs_phy.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Meta
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PHY_STM32U5_OTG_HS_PHY_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PHY_STM32U5_OTG_HS_PHY_H_
+
+#define OTGHS_PHY_CLK_16MHZ   1
+#define OTGHS_PHY_CLK_19P2MHZ 2
+#define OTGHS_PHY_CLK_20MHZ   3
+#define OTGHS_PHY_CLK_24MHZ   4
+#define OTGHS_PHY_CLK_26MHZ   5
+#define OTGHS_PHY_CLK_32MHZ   6
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PHY_STM32U5_OTG_HS_PHY_H_ */