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Document how to use the HSE clock as the source, and USB on the STM32 Nucleo U5A5ZJ-Q board #79825

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erikarn opened this issue Oct 15, 2024 · 0 comments
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area: Documentation Enhancement Changes/Updates/Additions to existing features platform: STM32 ST Micro STM32

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@erikarn
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erikarn commented Oct 15, 2024

Is your enhancement proposal related to a problem? Please describe.

The current nucleo board description (https://docs.zephyrproject.org/latest/boards/st/nucleo_u5a5zj_q/doc/index.html) and support doesn't enable USB-HS. Enabling USB-HS requires that specific components are stuffed including X4, a 16MHz crystal feeding the HSE clock.

However, at least on the board /I/ just bought, they're already stuffed! So it's very possible to enable it by default.
I have some working diffs locally; I need to clean them up and post them.

The TL;DR though is:

  • add the HSE clock source in the device-tree
+/* This board has a 16MHz crystal attached */
+&clk_hse {
+        clock-frequency = <DT_FREQ_M(16)>;
+        status = "okay";
+};
+
  • add a suitable "zephyr_udc0", matching what another u5 part did (just make sure you use the HS pinmux, eg)
+zephyr_udc0: &usbotg_hs {
+        pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
+        pinctrl-names = "default";
+        status = "okay";
+};
  • add the HSE clock source rather the internal RC source, by changing pll1)
+&pll1 {
+       /* HSE 16MHz source, outputting 160MHz to sysclk and apbclk */
+       div-m = <4>; /* input divisor */
+       mul-n = <80>; /* VCO multiplication factor */
+       div-q = <2>; /* system clock divisor */
+       div-r = <2>; /* peripheral clock divisor */
+       clocks = <&clk_hse>;
+       status = "okay";
+};

And then for the CDC-ACM demo, add this to samples/subsys/usb/cdc_acm/nucleo_u5a5zj_q.overlay:

/*
 * Copyright (c) 2023 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

zephyr_udc0: &usbotg_hs {
	status = "okay";
	cdc_acm_uart0 {
		compatible = "zephyr,cdc-acm-uart";
	};
};

Then it can be built like normal, ie:

`

west build -b nucleo_u5a5zj_q samples/subsys/usb/cdc_acm

`

Describe the solution you'd like

I'm not sure yet. I'm worried that there are versions of the Nucleo board without the HSE crystal (X4) stuffed and jumpered correctly. Is it worth creating a separate board type that assumes it's populated? Or just assume they are and document in the device tree how to flip just to the RC clock source if someone has a board without it?

Describe alternatives you've considered

(n/a)

Additional context

@erikarn erikarn added the Enhancement Changes/Updates/Additions to existing features label Oct 15, 2024
@nordicjm nordicjm added the platform: STM32 ST Micro STM32 label Oct 15, 2024
erikarn pushed a commit to erikarn/zephyr that referenced this issue Dec 3, 2024
…5xxx

The existing code assumes that the HSE clock is a 16MHz crystal, however
the hardware allows for a list of possible HSE clock values.

Add them here as an enum, configure it for the STM32U595 chipset
(which is the only device I have access to for testing).

This addresses Issue zephyrproject-rtos#79825 .

* Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the
  stm32u5 CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
* Add a list of possible values to use in the DT bindings directory
* Add a new PHY (st,stm32-otghs-phy) with an enum list matching the
  above list
* Add support in the USB driver for checking the clock-cfg entry
  and compiling in the correct clock rate.
* And also handle an out of enum configuration by failing compilation.

Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
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