boards: s32z270: enable support psi5

enable support psi5 Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
zephyrproject-rtos · Dec 12, 2024 · 8c85820 · 8c85820
1 parent 16f5942
commit 8c85820
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diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst
@@ -60,6 +60,9 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | DSPI      | on-chip    | spi                                 |
 +-----------+------------+-------------------------------------+
++-----------+------------+-------------------------------------+
+| PSI5      | on-chip    | psi5                                 |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 

diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
@@ -1259,5 +1259,76 @@
 			status = "disabled";
 		};
 
+		psi5_0: psi5@401e0000 {
+			compatible = "nxp,s32-psi5";
+			reg = <0x401e0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			psi5_0_ch0: ch@0 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <0>;
+				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch1: ch@1 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <1>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch2: ch@2 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <2>;
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch3: ch@3 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <3>;
+				interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+		};
+
+		psi5_1: psi5@421e0000 {
+			compatible = "nxp,s32-psi5";
+			reg = <0x421e0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			psi5_1_ch0: ch@0 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <0>;
+				interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch1: ch@1 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <1>;
+				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch2: ch@2 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <2>;
+				interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch3: ch@3 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <3>;
+				interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+		};
 	};
 };
diff --git a/west.yml b/west.yml
@@ -199,7 +199,7 @@ manifest:
       groups:
         - hal
     - name: hal_nxp
-      revision: c9f73c70d921b3fdea0c646bd76a2a4f5a23e7f0
+      revision: pull/451/head
       path: modules/hal/nxp
       groups:
         - hal
-Original file line number
+Diff line change
@@ Expand Up / @@ -60,6 +60,9 @@ The boards support the following hardware features: @@
     +-----------+------------+-------------------------------------+
     | DSPI      | on-chip    | spi                                 |
     +-----------+------------+-------------------------------------+
+    +-----------+------------+-------------------------------------+
+    | PSI5      | on-chip    | psi5                                 |
+    +-----------+------------+-------------------------------------+
     Other hardware features are not currently supported by the port.
@@ Expand Down @@