Remove explicit VEX coding from sad ASM (#2941)

* Remove explicit VEX coding from sad ASM
xiph · May 16, 2022 · 9d6d5d1 · 9d6d5d1
1 parent 9c3a494
commit 9d6d5d1
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/x86/sad_row.asm b/src/x86/sad_row.asm
@@ -71,7 +71,7 @@ cglobal sad_row_8bpc, 3, 5, 8, p1, p2, len, \
   add     p2q, lenq
   sub     resid_simdq, lenq
   ; last register needed for unrolled loop
-  vpxor   xm3, xm3
+  pxor    xm3, xm3
   neg     lenq
 .loop:
   mova        m4,     [p1q + lenq + 0*mmsize]
@@ -92,7 +92,7 @@ cglobal sad_row_8bpc, 3, 5, 8, p1, p2, len, \
   add         lenq, 4*mmsize
   jnz        .loop
 
-  vpaddq      m2, m3
+  paddq       m2, m3
 .lt_4x:
   ; jump to correct place for residual vector reduction
   test      resid_simdd, resid_simdd