Merge pull request #2608 from verilog-to-routing/enable_simple_place_…

…delay_matrix Use Simple Place Delay Model By Default
verilog-to-routing · Jul 5, 2024 · b00967c · b00967c
2 parents 9ddb7d5 + 1a6bb5e
commit b00967c
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Showing 63 changed files with 3,210 additions and 3,121 deletions.
diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp
@@ -2276,7 +2276,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
             " * 'simple' uses map router lookahead\n"
             " * 'delta' uses differences in position only\n"
             " * 'delta_override' uses differences in position with overrides for direct connects\n")
-        .default_value("delta")
+        .default_value("simple")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
     place_timing_grp.add_argument<e_reducer, ParseReducer>(args.place_delay_model_reducer, "--place_delay_model_reducer")
@@ -3065,6 +3065,13 @@ void set_conditional_defaults(t_options& args) {
         }
     }
 
+    // If MAP Router lookahead is not used, we cannot use simple place delay lookup
+    if (args.place_delay_model.provenance() != Provenance::SPECIFIED) {
+        if (args.router_lookahead_type != e_router_lookahead::MAP) {
+            args.place_delay_model.set(PlaceDelayModelType::DELTA, Provenance::INFERRED);
+        }
+    }
+
     // Check for correct options combinations
     // If you are running WLdriven placement, the RL reward function should be
     // either basic or nonPenalizing basic

diff --git a/...low/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width_small.txt b/...low/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width_small.txt
@@ -0,0 +1,16 @@
+#VPR metrics at fixed channel width
+
+#Area metrics
+logic_block_area_total;Range(0.5,1.6)
+logic_block_area_used;Range(0.5,1.6)
+routing_area_total;Range(0.5,1.6)
+routing_area_per_tile;Range(0.5,1.6)
+
+#Run-time metrics
+crit_path_route_time;RangeAbs(0.10,10.0,2)
+
+#Peak memory
+#We set a 100MiB minimum threshold since the memory 
+#alloctor (e.g. TBB vs glibc) can cause a difference
+#particularly on small benchmarks
+max_vpr_mem;RangeAbs(0.8,1.203,102400)
diff --git a/vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt b/vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt
@@ -0,0 +1,27 @@
+#VPR metrics at minimum channel width
+
+#Routing Metrics
+min_chan_width;Range(0.25,1.50)
+routed_wirelength;RangeAbs(0.50,1.50,5)
+
+#Area metrics
+logic_block_area_total;Range(0.5,1.6)
+logic_block_area_used;Range(0.5,1.6)
+min_chan_width_routing_area_total;Range(0.5,1.6)
+min_chan_width_routing_area_per_tile;Range(0.5,1.6)
+
+#Run-time metrics
+min_chan_width_route_time;RangeAbs(0.10,15.0,2)
+
+#Peak memory
+#We set a 100MiB minimum threshold since the memory 
+#alloctor (e.g. TBB vs glibc) can cause a difference
+#particularly on small benchmarks
+#
+#Note that due to different binary search path, peak memory
+#can differ significantly during binary search (e.g. a larger
+#or smaller channel width explored during the search can
+#significantly affect the size of the RR graph, and correspondingly
+#peak mememory usage in VPR. As a result we just a larger permissible
+#range for peak memory usage.
+max_vpr_mem;RangeAbs(0.5,2.0,102400)
diff --git a/...w/parse/pass_requirements/common/pass_requirements.vpr_route_relaxed_chan_width_small.txt b/...w/parse/pass_requirements/common/pass_requirements.vpr_route_relaxed_chan_width_small.txt
diff --git a/vtr_flow/parse/pass_requirements/pass_requirements_chain_small.txt b/vtr_flow/parse/pass_requirements/pass_requirements_chain_small.txt
@@ -0,0 +1,12 @@
+%include "common/pass_requirements.vpr_status.txt"
+%include "timing/pass_requirements.vpr_pack_place.txt"
+%include "timing/pass_requirements.vpr_route_min_chan_width_small.txt"
+%include "timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt"
+
+%include "common/pass_requirements.vtr_benchmarks.txt"
+
+num_luts;Range(0.9,1.10)
+num_add_blocks;Range(0.9,1.10)
+max_add_chain_length;Range(0.9,1.10)
+num_sub_blocks;Range(0.9,1.10)
+max_sub_chain_length;Range(0.9,1.10)
diff --git a/vtr_flow/parse/pass_requirements/pass_requirements_small.txt b/vtr_flow/parse/pass_requirements/pass_requirements_small.txt
@@ -0,0 +1,6 @@
+%include "common/pass_requirements.vpr_status.txt"
+%include "timing/pass_requirements.vpr_pack_place.txt"
+%include "timing/pass_requirements.vpr_route_min_chan_width_small.txt"
+%include "timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt"
+
+%include "common/pass_requirements.vtr_benchmarks.txt"
diff --git a/vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_min_chan_width_small.txt b/vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_min_chan_width_small.txt
@@ -0,0 +1,2 @@
+#VPR metrics at minimum channel width with timing
+%include "../common/pass_requirements.vpr_route_min_chan_width_small.txt"
diff --git a/...w/parse/pass_requirements/timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt b/...w/parse/pass_requirements/timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt
@@ -0,0 +1,19 @@
+#VPR metrix at relaxed (relative to minimum) channel width with timing
+%include "../common/pass_requirements.vpr_route_relaxed_chan_width_small.txt"
+
+#Routing Metrics
+crit_path_routed_wirelength;Range(0.40,1.60)
+
+#Area Metrics
+crit_path_routing_area_total;Range(0.5,1.5)
+crit_path_routing_area_per_tile;Range(0.5,1.5)
+
+#Run-time Metrics
+crit_path_route_time;RangeAbs(0.10,10.0,2)
+#Timing Metrics
+critical_path_delay;Range(0.40,1.60)
+geomean_nonvirtual_intradomain_critical_path_delay;Range(0.40,1.60)
+setup_TNS;Range(0.40,1.60)
+setup_WNS;Range(0.40,1.60)
+#hold_TNS;Range(0.05,20.00)
+#hold_WNS;Range(0.05,20.00)
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt
@@ -1,9 +1,9 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	crit_path_total_internal_heap_pushes	crit_path_total_internal_heap_pops	crit_path_total_external_heap_pushes	crit_path_total_external_heap_pops	crit_path_total_external_SOURCE_pushes	crit_path_total_external_SOURCE_pops	crit_path_total_internal_SOURCE_pushes	crit_path_total_internal_SOURCE_pops	crit_path_total_external_SINK_pushes	crit_path_total_external_SINK_pops	crit_path_total_internal_SINK_pushes	crit_path_total_internal_SINK_pops	crit_path_total_external_IPIN_pushes	crit_path_total_external_IPIN_pops	crit_path_total_internal_IPIN_pushes	crit_path_total_internal_IPIN_pops	crit_path_total_external_OPIN_pushes	crit_path_total_external_OPIN_pops	crit_path_total_internal_OPIN_pushes	crit_path_total_internal_OPIN_pops	crit_path_total_external_CHANX_pushes	crit_path_total_external_CHANX_pops	crit_path_total_internal_CHANX_pushes	crit_path_total_internal_CHANX_pops	crit_path_total_external_CHANY_pushes	crit_path_total_external_CHANY_pops	crit_path_total_internal_CHANY_pushes	crit_path_total_internal_CHANY_pops	crit_path_rt_node_SOURCE_pushes	crit_path_rt_node_SINK_pushes	crit_path_rt_node_IPIN_pushes	crit_path_rt_node_OPIN_pushes	crit_path_rt_node_CHANX_pushes	crit_path_rt_node_CHANY_pushes	crit_path_adding_all_rt	crit_path_adding_high_fanout_rt	crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
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 k6_N10_mem32K_40nm.xml	single_wire.v	common	0.53	vpr	60.99 MiB		-1	-1	0.10	19712	1	0.01	-1	-1	32156	-1	-1	0	1	0	0	success	v8.0.0-7648-g96837b3-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:14:09	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	62452	1	1	1	2	0	1	2	3	3	9	-1	auto	22.2 MiB	0.00	2	61.0 MiB	0.00	0.00	0.205011	-0.205011	-0.205011	nan	0.01	6.508e-06	4.21e-06	4.7302e-05	3.2578e-05	2	1	1	53894	0	1165.58	129.509	0.00	0.000133792	9.5007e-05	254	297	-1	1	1	1	1	17	8	0	0	17	8	1	1	0	0	4	1	0	0	8	4	0	0	1	1	0	0	2	1	0	0	1	0	0	0	1	0	0	0	0	0	1	0	0	0.211201	nan	-0.211201	-0.211201	0	0	1165.58	129.509	0.00	0.00	0.00	-1	-1	0.00	6.1111e-05	4.4458e-05	
 k6_N10_mem32K_40nm.xml	single_wire.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	0.58	vpr	61.23 MiB		-1	-1	0.13	19728	1	0.00	-1	-1	32200	-1	-1	0	1	0	0	success	v8.0.0-7648-g96837b3-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:14:09	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	62696	1	1	1	2	0	1	2	3	3	9	-1	auto	22.4 MiB	0.00	2	61.2 MiB	0.00	0.00	0.205011	-0.205011	-0.205011	nan	0.01	6.184e-06	3.993e-06	4.3641e-05	2.9251e-05	2	1	1	53894	0	1165.58	129.509	0.00	0.000125688	8.6197e-05	254	297	-1	1	1	1	1	17	8	0	0	17	8	1	1	0	0	4	1	0	0	8	4	0	0	1	1	0	0	2	1	0	0	1	0	0	0	1	0	0	0	0	0	1	0	0	0.211201	nan	-0.211201	-0.211201	0	0	1165.58	129.509	0.00	0.00	0.00	-1	-1	0.00	6.1706e-05	4.4581e-05	
-k6_N10_mem32K_40nm.xml	single_ff.v	common	0.58	vpr	61.16 MiB		-1	-1	0.15	20380	1	0.00	-1	-1	32344	-1	-1	1	2	0	0	success	v8.0.0-7648-g96837b3-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:14:09	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	62628	2	1	3	4	1	3	4	3	3	9	-1	auto	22.3 MiB	0.00	4	61.2 MiB	0.00	0.00	0.570641	-0.944653	-0.570641	0.570641	0.01	8.111e-06	5.609e-06	6.9436e-05	5.2818e-05	2	4	2	53894	53894	1165.58	129.509	0.00	0.000214692	0.000163548	254	297	-1	4	2	3	3	75	50	0	0	75	50	3	3	0	0	18	17	0	0	18	18	0	0	21	3	0	0	7	6	0	0	8	3	0	0	3	0	0	0	0	0	3	0	0	0.577715	0.577715	-1.12352	-0.577715	0	0	1165.58	129.509	0.00	0.00	0.00	-1	-1	0.00	0.000126735	9.9717e-05	
-k6_N10_mem32K_40nm.xml	single_ff.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	0.53	vpr	61.28 MiB		-1	-1	0.10	20236	1	0.00	-1	-1	32312	-1	-1	1	2	0	0	success	v8.0.0-7648-g96837b3-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:14:09	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	62752	2	1	3	4	1	3	4	3	3	9	-1	auto	22.4 MiB	0.00	4	61.3 MiB	0.00	0.00	0.570641	-0.944653	-0.570641	0.570641	0.01	8.326e-06	5.482e-06	6.6158e-05	4.802e-05	2	4	2	53894	53894	1165.58	129.509	0.00	0.000213451	0.000160083	254	297	-1	4	2	3	3	75	50	0	0	75	50	3	3	0	0	18	17	0	0	18	18	0	0	21	3	0	0	7	6	0	0	8	3	0	0	3	0	0	0	0	0	3	0	0	0.577715	0.577715	-1.12352	-0.577715	0	0	1165.58	129.509	0.00	0.00	0.00	-1	-1	0.00	0.000106785	8.5521e-05	
+k6_N10_mem32K_40nm.xml	single_ff.v	common	0.58	vpr	61.16 MiB		-1	-1	0.15	20380	1	0.00	-1	-1	32344	-1	-1	1	2	0	0	success	v8.0.0-7648-g96837b3-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:14:09	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	62628	2	1	3	4	1	3	4	3	3	9	-1	auto	22.3 MiB	0.00	4	61.2 MiB	0.00	0.00	0.570641	-0.944653	-0.570641	0.570641	0.01	8.111e-06	5.609e-06	6.9436e-05	5.2818e-05	2	4	2	53894	53894	1165.58	129.509	0.00	0.000214692	0.000163548	254	297	-1	3	2	3	3	75	50	0	0	75	50	3	3	0	0	18	17	0	0	18	18	0	0	21	3	0	0	7	6	0	0	8	3	0	0	3	0	0	0	0	0	3	0	0	0.577715	0.577715	-1.12352	-0.577715	0	0	1165.58	129.509	0.00	0.00	0.00	-1	-1	0.00	0.000126735	9.9717e-05	
+k6_N10_mem32K_40nm.xml	single_ff.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	0.53	vpr	61.28 MiB		-1	-1	0.10	20236	1	0.00	-1	-1	32312	-1	-1	1	2	0	0	success	v8.0.0-7648-g96837b3-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:14:09	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	62752	2	1	3	4	1	3	4	3	3	9	-1	auto	22.4 MiB	0.00	4	61.3 MiB	0.00	0.00	0.570641	-0.944653	-0.570641	0.570641	0.01	8.326e-06	5.482e-06	6.6158e-05	4.802e-05	2	4	2	53894	53894	1165.58	129.509	0.00	0.000213451	0.000160083	254	297	-1	3	2	3	3	75	50	0	0	75	50	3	3	0	0	18	17	0	0	18	18	0	0	21	3	0	0	7	6	0	0	8	3	0	0	3	0	0	0	0	0	3	0	0	0.577715	0.577715	-1.12352	-0.577715	0	0	1165.58	129.509	0.00	0.00	0.00	-1	-1	0.00	0.000106785	8.5521e-05
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		#VPR metrics at minimum channel width with timing
		%include "../common/pass_requirements.vpr_route_min_chan_width_small.txt"