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Add Verilog blackbox FireSim simulation example #297

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Oct 16, 2019
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Add Verilog blackbox FireSim simulation example #297

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b862c66
Add Verilog blackbox FireSim simulation example
albert-magyar Oct 12, 2019
6256641
Update build.sbt
albert-magyar Oct 14, 2019
cf9a936
Revert to dev firesim pointer
albert-magyar Oct 16, 2019
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2 changes: 1 addition & 1 deletion build.sbt
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Original file line number Diff line number Diff line change
Expand Up @@ -189,7 +189,7 @@ lazy val midas = ProjectRef(firesimDir, "midas")
lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")

lazy val firechip = (project in file("generators/firechip"))
.dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
.dependsOn(example, icenet, testchipip, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
.settings(
commonSettings,
testGrouping in Test := isolateAllTests( (definedTests in Test).value )
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12 changes: 12 additions & 0 deletions generators/firechip/src/main/scala/Targets.scala
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Expand Up @@ -101,3 +101,15 @@ class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModu

// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1
class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)

// Verilog blackbox integration demo
class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT
with example.HasPeripheryGCD
{
override lazy val module = new FireSimVerilogGCDModuleImp(this)
}

class FireSimVerilogGCDModuleImp[+L <: FireSimVerilogGCDDUT](l: L) extends FireSimModuleImp(l)
with example.HasPeripheryGCDModuleImp

class FireSimVerilogGCD(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimVerilogGCDDUT)