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PLL integration example + FlatChipTop/TestHarness #1427
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Looks good for the most part without testing.
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Does this require/assume the PLL is actually a PLL (because internal clock/external clock edges need to be synchronous or something), or could some other clock multiplier be inserted instead? |
The |
WithPLLSelectorDividerClockGenerator
to replace the defaultWithDividerOnlyClockGenerator
. WithPLLSelectorDividerClockGenerator adds regmapped clock-mux, clock-divider, and a fake PLL with regmapped control. The intention is for future chips to create custom clock binders following this patternChipConfigs
file withChipLikeRocketConfig
, that sets up crossings, clock gen, I/O more realistically.FlatChipTop
andFlatTestHarness
, to demonstrate how to use a custom TestHarness+ChipTop with Chipyard, bypassing the IOBinders/HarnessBinders if necessary (this should only be done as a last resort).For custom ChipTop/TestHarness... do
Related PRs / Issues:
Type of change:
Impact:
Contributor Checklist:
main
as the base branch?changelog:<topic>
label?changelog:
label?.conda-lock.yml
file if you updated the conda requirements file?Please Backport
?