Add build of ChipLikeQuadRocketConfig to CI

ucb-bar · Apr 8, 2023 · de293f5 · de293f5
1 parent b88e102
commit de293f5
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Showing 5 changed files with 9 additions and 8 deletions.
diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
@@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 # key value store to get the build groups
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike"
 grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -53,6 +53,7 @@ mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
 mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
 mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
+mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig verilog"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"

diff --git a/generators/chipyard/src/main/scala/HarnessClocks.scala b/generators/chipyard/src/main/scala/HarnessClocks.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Field, Parameters, Config}
+import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci._
 

diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -4,7 +4,7 @@ import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy._
 
 // A simple config demonstrating how to set up a basic chip in Chipyard
-class ChipLikeRocketConfig extends Config(
+class ChipLikeQuadRocketConfig extends Config(
   //==================================
   // Set up TestHarness
   //==================================

diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -2,7 +2,7 @@ package chipyard.example
 
 
 import chisel3._
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util._
@@ -102,10 +102,10 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
     //=========================
     // JTAG/Debug
     //=========================
-    val debug = system.module.debug.get
+    val debug = system.debug.get
     // We never use the PSDIO, so tie it off on-chip
-    system.module.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
-    system.module.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } }
+    system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
+    system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } }
 
     // Tie off extTrigger
     debug.extTrigger.foreach { t =>

diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters}
 import freechips.rocketchip.util.{PlusArg}