Add comments on ResetStretchers

ucb-bar · Apr 8, 2023 · b88e102 · b88e102
1 parent b7b2a62
commit b88e102
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diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
@@ -41,6 +41,8 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
 
       // Note this is not synchronized to the output clock, which takes time to appear
       // so this is still asyncreset
+      // Stretch the reset for 40 cycles, to give enough time to reset any downstream
+      // digital logic
       sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
       reg
     }

diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
@@ -59,6 +59,7 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e
       mux.io.sel        := sel
       mux.io.resetAsync := asyncReset.asAsyncReset
       sinks(i).clock := mux.io.clockOut
+      // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
       sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
 
       reg