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verilog

Here are 64 public repositories matching this topic...

pavel-demin / red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

radio linux fpga zynq dsp tcl verilog nmr xilinx sdr mca redpitaya vna vivado wspr red-pitaya vitis

Updated Feb 27, 2025
Tcl

d953i / Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

csv fpga ddr tcl calibration verilog xilinx vivado mig axi sqrl ddr4 vcu1525 bcu1525 dimm udimm rdimm sodimm

Updated Feb 4, 2024
Tcl

kkiningh / cs231n-project

CNN accelerator

verilog convolutional-neural-networks cs231n hardware-acceleration

Updated Jun 11, 2017
Tcl

Essenceia / ethernet-physical-layer

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

c fpga rtl verilog ethernet iverilog vpi pcs 10gbase-r 40gbase-r

Updated Jan 2, 2024
Tcl

stineje / sky130_cds

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

eda verilog vlsi cadence skywater

Updated Jul 25, 2023
Tcl

LSC-Unicamp / processor-ci-controller

Controller module for RISC-V core CI/CD

fpga riscv verilog

Updated Apr 7, 2025
Tcl

icglue / icglue

A Tcl-Library for scripted HDL generation

verilog systemverilog hdl verilog-hdl systemverilog-hdl tcl-applications

Updated Apr 30, 2024
Tcl

Choaib-ELMADI / fpga-programming-for-beginners

A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.

embedded fpga electronics vhdl embedded-systems verilog systemverilog fpga-soc fpga-board fpga-programming

Updated Aug 25, 2024
Tcl

kkiningh / synthesis-example

Example of a full DC synthesis script for a simple design

verilog synthesis synopsys vlsi designcompiler

Updated Feb 25, 2019
Tcl

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

verilog microprocessor vivado fibonacci-numbers 7-segment risc-v fibonacci-sequence basys3 vivado-hls artix-7 basys3-fpga single-cycle-processor basys3-fpga-board

Updated Dec 7, 2022
Tcl

avinashy2j / StaticTimingAnalysis

Implementation of Timing Exceptions in RTL design for STA

asic verilog tcl-scripts

Updated Sep 15, 2019
Tcl

suoglu / Divider

Hardware integer divider module

fpga hardware verilog divider

Updated Aug 3, 2023
Tcl

timothystotts / fpga-serial-acl-tester-3

A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.

fpga vhdl verilog systemverilog pmod zybo-z7 arty-s7 arty-a7 systemonchip

Updated Aug 10, 2024
Tcl

yunusesergun / yesergun.fpga.dev

All about FPGA...

fpga clock vhdl rtl verilog vivado axi4-protocol

Updated Nov 10, 2024
Tcl

marplyn / Processor-Systems-Architecture

МИЭТ, курс "Архитектуры процессорных систем"

vhdl verilog fgpa

Updated Dec 26, 2022
Tcl

RomeoMe5 / FPGA-Matrix-Base-operations

Matrix base operations on FPGA example

fpga verilog hse modelsim miem matrix-operations

Updated May 24, 2019
Tcl

Bucknalla / warc_fusesoc

WARC Open Fusesoc Cores Repository

hls ip verilog migen open-cores

Updated Mar 17, 2020
Tcl

aasthaasb / Parkingslot-manager

Implementing a parking slot system usingRTL Coding, the PYNQ Z2 board, seven-segment display, wires, and a breadboard.

electronics rtl verilog sensors digitalcircuit

Updated May 16, 2024
Tcl

suoglu / Simple-SPI

Set of simple modules to communicate using SPI protocol.

fpga verilog spi

Updated Nov 9, 2023
Tcl

JN513 / Baby-Risco-5

Multi-cycle RISC-V processor with RV32E implementation

riscv verilog verilog-hdl riscv32 riscv32e

Updated Oct 29, 2024
Tcl

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