open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

GPGPU microprocessor architecture

这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS

A Compiler for the Popr Language

Simple 3-stage pipeline RISC-V processor

PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities

客制化机械键盘——从0开始全套资料

FPGA 101 - Workshop materials

Small Processing Unit 32: A compact RV32I CPU written in Verilog

PDP-6 Emulator

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

High Speed USB 2.0 capture device based on miniSpartan6+

Homebrew game for homebrew FPGA game console

YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.

The collective code required for completing a 4-year B.Tech Computer Science Engineering Course.

SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

Pipelined RISC-V RV32I Core in Verilog

Generator of arithmetic circuits (multipliers, adders) and approximate circuits

This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog. Code in this repo contains both C++ SGBM simulation code and PS-PL vitis-vivado project. Tutorial and the video attached thoroughly explain my designation in detail, although made in Chinese hhhhh.

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)