systemverilog
Here are 10 public repositories matching this topic...
Functional verification project for the CORE-V family of RISC-V cores.
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Jan 31, 2025 - Assembly
RISC-V Zve32x Vector Coprocessor
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Dec 2, 2023 - Assembly
🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.
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Jan 23, 2025 - Assembly
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
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Nov 16, 2023 - Assembly
Snake game implemented in RISC-V assembly that runs on custom hardware, utilizing interrupts, MMIO ports, and a 160x120 VGA driver
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Dec 9, 2024 - Assembly
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Jun 21, 2019 - Assembly
Processor design project featuring 9-bit ISA 🤖
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Mar 16, 2022 - Assembly
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Mar 31, 2021 - Assembly
A tiny, open-source RISC-V processor designed for learning and experimentation.
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Jan 30, 2025 - Assembly
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