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jracevedob/README.md

Javier Acevedo

I am professional baseband system engineer in Dresden, Germany. I am mostly interested on designing and deploying versatile and agile state-of-the-art compute platforms for wireless communication systems. I am currently working on bringing hardware acceleration to the Radio Access Network (RAN), while integrating it with the Core Network.

Motto

It is better to die on your feet that live on your knees - Emiliano Zapata.

Main functional motivation

Hardware-Software Co-Design of the entire product development life cycle for 5G's RAN and Core Network.

Contact

You can contact me mainly via E-mail under the following address account.

Current projects

In this moement, we are working on two different projects about wireless communications and genetics.

  1. Hardware accelerated version of the Open RAN Intelligent Controller (RIC).
  2. Hardware accelerated version of the training sequence for protein folding. ESM Meta

Learning and traning

Currently, I am learning how to employ Svelt and Nx Monorepo to enhance frontend development. This is my first approach to frontend development.

News

rApps: the Non Real Time RAN Intelligent Controller (RIC) represents a great opportunity for innovation in wireless communication networks. I have had the pleasure to start working on the Open RAN Software Community with the target in mind of being able to develop rApps to control the whole RAN.

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Popular repositories Loading

  1. Post-Shannon-SDR Post-Shannon-SDR Public

    In this repository, you will find the source code for analyzing tracks during data transmission using Software Defined Radios. Metrics about error positioning and error syndrome are attached.

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  2. Processor-Design Processor-Design Public

    In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilo…

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  3. MPSoC_Networking MPSoC_Networking Public

    This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)

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  4. TheFifthDriverAI TheFifthDriverAI Public

    The Fifth Driver is a project for the Adaptative Computing Developer Contest for Xilinx. We pretend to demonstrate that the Xilinx Ultrascale+ MPSoC architecture is suitable for developing machine …

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  5. composite_finite_fields composite_finite_fields Public

    In this directoy, you will find a composite finite field calculator for different matrix sizes. The default matrix size will deal with Galois fields GF(2), but the calculation will scale up to infi…

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  6. OrchestRAN OrchestRAN Public

    This repository contains the findings for scheduling heterogeneous payloads within the Distributed Unit (DU) of a 5G Radio Access Network (RAN)

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