Open-source high-performance RISC-V processor
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Jan 22, 2025 - Scala
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risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 39 public repositories matching this topic...
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha
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Jan 20, 2025 - Scala
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
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Jan 13, 2025 - Scala
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
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Jun 25, 2020 - Scala
A fault-injection framework using Chisel and FIRRTL
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Feb 1, 2023 - Scala
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.
fpga rocket-chip xilinx fpga-soc risc-v xilinx-fpga bitstream digilent e300 sifive artix-100t sifive-freedom arty-a7 artix-35t
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Jan 23, 2024 - Scala
Network components (NIC, Switch) for FireBox
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Oct 27, 2024 - Scala
Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"
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Jul 30, 2019 - Scala
BOOM's Simulation Accelerator.
simulation accelerator boom rocket rocket-chip chisel riscv rtl firrtl soc risc-v verilator chipyard
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Dec 16, 2021 - Scala
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
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Jul 30, 2019 - Scala
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
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Jan 19, 2022 - Scala