pynq-z2

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RTL and python for using the ADAU1761 audio codec on the Pynq-Z2 board from TUL

audio i2s-audio pynq-z2

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

sdk fpga hardware accelerator matrix project matrix-multiplication verilog xilinx vivado systemverilog hardware-designs hdl hardware-acceleration zynq-7000 systolic-arrays pynq-z2 vitis

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