fsm
A finite-state machine (FSM), finite-state automaton (FSA), or simply state machine is a mathematical model of computation and an abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some inputs; the change from one state to another is called a transition.
An FSM is defined by a list of its states, its initial state, and the inputs that trigger each transition.
In computer science, FSM are widely used in modeling of application behavior (control theory), design of hardware digital systems, software engineering, compilers, network protocols, and computational linguistics.
Here are 33 public repositories matching this topic...
Human Resource Machine - CPU Design #HRM
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Feb 14, 2021 - Verilog
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
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Sep 15, 2023 - Verilog
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
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May 10, 2019 - Verilog
Digital Logic Design course project , Fall of 2024
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Jan 15, 2025 - Verilog
A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board
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Dec 9, 2018 - Verilog
This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with single port sync RAM.
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Jan 31, 2025 - Verilog
This repository contains a collection of small Verilog modules for various purposes.
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Aug 13, 2024 - Verilog
Complex Adder with Seven Segment Display
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Apr 24, 2018 - Verilog
Desenvolvimento de uma aplicação sobre sobre Máquina de Estados Finita, desenvolvida nos dois modelos de comunicação: Síncrona e Assíncrona, para a disciplina de Arquitetura de Computadores II Unisinos-2019.
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Mar 28, 2019 - Verilog
RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.
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Aug 3, 2024 - Verilog
FSM: Sequence Detector using Verilog HDL
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Jul 12, 2024 - Verilog
Verilog Programs
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Apr 16, 2021 - Verilog
Using finite state machine (FSM) approach to design a traffic light controller on Altera DE1 development board.
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Dec 8, 2019 - Verilog
Traffic Light Controller This repository showcases the design and implementation of a Traffic Light Controller using Verilog. The project simulates a real-world traffic management system, ensuring smooth vehicle movement at intersections through an efficient state-based control mechanism.
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Jan 6, 2025 - Verilog
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Aug 20, 2022 - Verilog
Final project for an advanced course in computer architecture, involving a full processor design and assembly code to run a game of Tic-Tac-Toe
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Nov 1, 2017 - Verilog
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