Reword the ASR description to clarify Zstid register behaviour. (risc…

…v#335)

The thread id registers introduced in Zstid differ in behaviour with
other registers in that they have different behaviour for reads than
writes, and the utidc register is treated as privileged for the purposes
of ASR checking. Try and clarify this more.

---------

Co-authored-by: Andrés Amaya Garcia <andres.amaya@codasip.com>

src/cap-description.adoc

@@ -120,10 +120,11 @@ Execute Permission (X):: Allow instruction execution.
 
 [#asr_perm,reftext="ASR-permission"]
 Access System Registers Permission (ASR):: Allow read and write access to all
-privileged (M-mode and S-mode) CSRs with the following exceptions:
-. <<utid>>, <<utidc>>, <<stid>>, <<stidc>>, <<mtid>>, <<mtidc>> all require ASR
-access for writing and not for reading, as well as having a suitable privileged
-execution mode.
+privileged (M-mode and S-mode) CSRs.
+If {tid_ext_name} is supported the <<utid>>, <<utidc>>, <<stid>>, <<stidc>>, <<mtid>>,
+<<mtidc>> registers are all considered privileged for the purposes of writing
+and unprivileged for reading, and thus require ASR-permission for writes but not reads.
+In all cases a suitable privilege mode is required for access.
 
 [#cap_permissions_encoding]
 ===== Permission Encoding