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Reword the ASR description to clarify Zstid register behaviour. #335

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merged 3 commits into from
Jul 29, 2024

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The thread id registers introduced in Zstid differ in behaviour with other registers in that they have different behaviour for reads than writes, and the utidc register is treated as privileged for the purposes of ASR checking. Try and clarify this more.

The thread id registers introduced in Zstid differ in behaviour with other
registers in that they have different behaviour for reads than writes, and the
utidc register is treated as privileged for the purposes of ASR checking. Try
and clarify this more.
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@andresag01 andresag01 merged commit 9d0b356 into riscv:main Jul 29, 2024
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tariqkurd-repo pushed a commit to tariqkurd-repo/riscv-cheri that referenced this pull request Oct 9, 2024
…v#335)

The thread id registers introduced in Zstid differ in behaviour with
other registers in that they have different behaviour for reads than
writes, and the utidc register is treated as privileged for the purposes
of ASR checking. Try and clarify this more.

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Co-authored-by: Andrés Amaya Garcia <andres.amaya@codasip.com>
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3 participants