[P2] Installation and Data Preloading Issue #11: new data type #68

yuqisun · 2025-01-19T10:22:24Z

I added a new type mk_cpu_pkt in messages.py to support both DataType and CtrlPktType, could you help review if I'm on the right way? This may impact many other RTLs as the ifc name changed.

And looks msg from CPU is not yet used in Tile right?

Thanks,

…e mk_cpu_pkt to support both data and ctrl type from cpu in one packet

tancheng · 2025-01-19T17:07:44Z

controller/ControllerRTL.py

-    s.recv_from_cpu_ctrl_pkt = RecvIfcRTL(CtrlPktType)
-    s.send_to_ctrl_ring_ctrl_pkt = SendIfcRTL(CtrlPktType)
+    s.recv_from_cpu_pkt = RecvIfcRTL(CpuPktType)
+    s.send_to_ctrl_ring_pkt = SendIfcRTL(CpuPktType)


Let's rename this to send_to_intra_cgra_pkt?

tancheng · 2025-01-19T17:09:05Z

controller/ControllerRTL.py

-    s.recv_from_cpu_ctrl_pkt = RecvIfcRTL(CtrlPktType)
-    s.send_to_ctrl_ring_ctrl_pkt = SendIfcRTL(CtrlPktType)
+    s.recv_from_cpu_pkt = RecvIfcRTL(CpuPktType)
+    s.send_to_ctrl_ring_pkt = SendIfcRTL(CpuPktType)

    # Request from/to tiles.
    s.recv_from_tile_load_request_pkt = RecvIfcRTL(NocPktType)


Let's rename this to recv_from_local_cgra_load_request_pkt?

tancheng · 2025-01-19T17:25:53Z

controller/ControllerRTL.py

@@ -102,6 +102,7 @@ def construct(s, ControllerIdType, CmdType, CtrlPktType, NocPktType,
      assert addr2controller_vector[addr_base] == -1, f"address range [{begin_addr}, {end_addr}] overlaps with others."
      addr2controller_vector[addr_base] = ControllerIdType(src_controller_id)

+      # What does this do? Connect itself?


This is to model/construct a look-up table (i.e., a map, a bunch of wires in HW) at design time to memorize the relationship between addr_base and controller_id.

Theoretically, this addr2controller_vector should also be delivered via cpu_pkt, and the look-up table should be updated accordingly. Can you please help create/file an issue for this?

tancheng · 2025-01-19T17:47:03Z

lib/messages.py

+def mk_cpu_pkt(datatype_id,
+               # DataType
+               payload_nbits=16, predicate_nbits=1, bypass_nbits=1,
+               # CtrlPktType
+               nrouters = 4, ctrl_actions = 8, ctrl_mem_size = 4, ctrl_operations = 7, ctrl_fu_inports = 4, ctrl_fu_outports = 4, ctrl_tile_inports = 5, ctrl_tile_outports = 5,
+               prefix="CPUPkt"):
+
+    if datatype_id == 0:
+        return mk_data(payload_nbits, predicate_nbits, bypass_nbits)
+    else:
+        return mk_ring_across_tiles_pkt(nrouters, ctrl_actions, ctrl_mem_size, ctrl_operations, ctrl_fu_inports, ctrl_fu_outports, ctrl_tile_inports, ctrl_tile_outports)


This is exactly same question as @yyan7223 asked: #69 (comment)

Instead of if/else here, I think we need to:

Rename mk_ring_across_tiles_pkt to mk_intra_cgra_pkt.

Extend mk_ring_across_tiles_pkt to have controller_id to make the pkt be able to traverse on the inter-cgra NoC for ctrl/const/data delivery @yyan7223.

Existing id in mk_ring_across_tiles_pkt is the tile_id, which is not enough to represent controller_id (or cgra_id).

Extend mk_ring_across_tiles_pkt to have data and data_addr for data memory write/initialization/over-write @yyan7223.

@yuqisun your const data can re-use this data field, as the const data and data memory's data should be the same bit-width/format.

Add another two types of CMD_XXX:

CMD_CONST: to indicate the pkt is for updating your ConstMemRTL.

CMD_CONST_CLEAR: to indicate the pkt is for updating your ConstMemRTL from wr_cur = 0, i.e., explicitly telling wr_cur go back to 0.

I am re-thinking about our discussion on whether we need to allow wr_cur goes back to 0. If we allow the 9th const data update the address 0 item (i.e., allowing wr_cur go back to 0 when size/limit is 8), we don't need this CMD_CONST_CLEAR to explicitly go back to 0. User should make sure reader is slower than writer, and make sure write less than size number of data. We can sync on this.

Your current implementation (if/else) would force the controller only accept either mk_data type or mk_ring_across_tiles_pkt type at design/model time, but not both.

How about renaming mk_ring_across_tiles_pkt to mk_preloading_cgra_pkt?

The pkt could be not only for preloading, it could be some dynamically generated pkt from CPU to guide some runtime behavior. So preloading sounds too narrow~?

Yeah, then I change it back

tancheng · 2025-01-19T17:50:34Z

controller/ControllerRTL.py

-    s.recv_from_cpu_ctrl_pkt //= s.recv_ctrl_pkt_queue.recv
-    s.recv_ctrl_pkt_queue.send //= s.send_to_ctrl_ring_ctrl_pkt
+    s.recv_from_cpu_pkt //= s.recv_pkt_queue.recv
+    s.recv_pkt_queue.send //= s.send_to_ctrl_ring_pkt


send_to_ctrl_ring_pkt -> send_to_intra_cgra_pkt.

tancheng · 2025-01-19T17:51:41Z

systolic/CgraSystolicArrayRTL.py


    # Connects ring with each control memory.
    for i in range(s.num_tiles):
      s.ctrl_ring.send[i] //= s.tile[i].recv_ctrl_pkt

-    s.ctrl_ring.recv[0] //= s.controller.send_to_ctrl_ring_ctrl_pkt
+    s.ctrl_ring.recv[0] //= s.controller.send_to_ctrl_ring_pkt


s.controller.send_to_ctrl_ring_pkt -> s.controller.send_to_intra_cgra_pkt.

tancheng · 2025-01-19T18:26:51Z

And looks msg from CPU is not yet used in Tile right?

msg from CPU is sent into the recv_pkt_queue in tile's ctrl_memory

VectorCGRA/mem/ctrl/CtrlMemDynamicRTL.py

Line 53 in 7222dae

s.recv_pkt //= s.recv_pkt_queue.recv

You are right, instead blindly connect it to tile's s.ctrl_mem.recv_pkt, we should connect the msg to both ctrl_mem and your new ConstMemRTL (will replacing this one). sth like:

@update
def feed_pkt():
  s.ctrl_mem.recv_pkt.msg @= SomeType(0)
  s.const_mem.recv_const.msg @= DataType(0)
  s.ctrl_mem.recv_pkt.val @= 0
  s.const_mem.recv_const.val @= 0
  s.recv_ctrl_pkt.rdy @= 0

  if s.recv_ctrl_pkt.val & (s.recv_ctrl_pkt.cmd_action == CMD_CONFIG):
    s.ctrl_mem.recv_pkt.val @= 1
    s.ctrl_mem.recv_pkt.msg @= s.recv_ctrl_pkt.msg
    s.recv_ctrl_pkt.rdy @= 1

  elif s.recv_ctrl_pkt.val & (s.recv_ctrl_pkt.cmd_action == CMD_CONST):
    s.const_mem.recv_pkt.val @= 1
    s.const_mem.recv_const.msg @= DataType(s.recv_ctrl_pkt.msg.data)
    s.recv_ctrl_pkt.rdy @= 1

…ables to more meaningful

… for const

…_pkt

lib/messages.py

tancheng · 2025-02-06T23:35:04Z

Hi Yuqi, is there still any blocker for this?

yuqisun · 2025-02-08T03:02:23Z

Hi Yuqi, is there still any blocker for this?

Thanks Cheng, I'm working on TileRTL, concern with it may impact others, will raise if any specific question.

tancheng · 2025-02-08T05:37:13Z

Hi Yuai,

VectorCGRA/tile/test/TileRTL_test.py

Lines 141 to 143 in 7222dae

    
           mk_separate_ctrl(num_ctrl_operations, num_fu_inports, 
        
                            num_fu_outports, num_tile_inports, 
        
                            num_tile_outports)

corresponds the ctrl definition you shared.

On the other hand,

VectorCGRA/tile/test/TileRTL_test.py

Lines 146 to 152 in 7222dae

    
           CtrlPktType(0,  0,  0,    0,  CMD_CONFIG, 0,   OPT_NAH,  b1(0), pick_register0, 
        
                       # routing_xbar_output 
        
                       [TileInType(0), TileInType(0), TileInType(0), TileInType(0), 
        
                        TileInType(4), TileInType(3), TileInType(0), TileInType(0)], 
        
                       # fu_xbar_output 
        
                       [FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), 
        
                        FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)]),

ordering is here:

VectorCGRA/lib/messages.py

Lines 214 to 238 in dbe6b94

    
           field_dict['ctrl'] = OperationType 
        
           # TODO: need fix to pair `predicate` with specific operation. 
        
           # The 'predicate' indicates whether the current operation is based on 
        
           # the partial predication or not. Note that 'predicate' is different 
        
           # from the following 'predicate_in', which contributes to the 'predicate' 
        
           # at the next cycle. 
        
           field_dict['predicate'] = PredicateType 
        
           # The fu_in indicates the input register ID (i.e., operands) for the 
        
           # operation. 
        
           field_dict['fu_in'] = [FuInType for _ in range(num_fu_inports)] 
        
           field_dict['routing_xbar_outport'] = [TileInportsType for _ in range( 
        
               num_routing_outports)] 
        
           field_dict['fu_xbar_outport'] = [FuOutType for _ in range( 
        
               num_routing_outports)] 
        
           # I assume one tile supports single predicate during the entire execution 
        
           # time, as it is hard to distinguish predication for different operations 
        
           # (we automatically update, i.e., 'or', the predicate stored in the 
        
           # predicate register). This should be guaranteed by the compiler. 
        
           field_dict['routing_predicate_in'] = [PredicateType for _ in range( 
        
               num_tile_inports)] 
        
           field_dict['vector_factor_power'] = VectorFactorPowerType 
        
           field_dict['is_last_ctrl'] = b1

tancheng · 2025-02-08T05:37:30Z

Good question btw!

yuqisun · 2025-02-08T06:10:49Z

Hi Yuai,

VectorCGRA/tile/test/TileRTL_test.py

Lines 141 to 143 in 7222dae

mk_separate_ctrl(num_ctrl_operations, num_fu_inports,

num_fu_outports, num_tile_inports,

num_tile_outports)

corresponds the ctrl definition you shared.

On the other hand,

VectorCGRA/tile/test/TileRTL_test.py

Lines 146 to 152 in 7222dae

CtrlPktType(0, 0, 0, 0, CMD_CONFIG, 0, OPT_NAH, b1(0), pick_register0,

# routing_xbar_output

[TileInType(0), TileInType(0), TileInType(0), TileInType(0),

TileInType(4), TileInType(3), TileInType(0), TileInType(0)],

# fu_xbar_output

[FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0),

FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)]),

ordering is here:

VectorCGRA/lib/messages.py

Lines 214 to 238 in dbe6b94

field_dict['ctrl'] = OperationType

# TODO: need fix to pair `predicate` with specific operation.

# The 'predicate' indicates whether the current operation is based on

# the partial predication or not. Note that 'predicate' is different

# from the following 'predicate_in', which contributes to the 'predicate'

# at the next cycle.

field_dict['predicate'] = PredicateType

# The fu_in indicates the input register ID (i.e., operands) for the

# operation.

field_dict['fu_in'] = [FuInType for _ in range(num_fu_inports)]

field_dict['routing_xbar_outport'] = [TileInportsType for _ in range(

num_routing_outports)]

field_dict['fu_xbar_outport'] = [FuOutType for _ in range(

num_routing_outports)]

# I assume one tile supports single predicate during the entire execution

# time, as it is hard to distinguish predication for different operations

# (we automatically update, i.e., 'or', the predicate stored in the

# predicate register). This should be guaranteed by the compiler.

field_dict['routing_predicate_in'] = [PredicateType for _ in range(

num_tile_inports)]

field_dict['vector_factor_power'] = VectorFactorPowerType

field_dict['is_last_ctrl'] = b1

Thanks, just found it 👍

yuqisun added 2 commits January 19, 2025 17:57

[P2] Installation and Data Preloading Issue tancheng#11: add new typ…

103493e

…e mk_cpu_pkt to support both data and ctrl type from cpu in one packet

[P2] Installation and Data Preloading Issue tancheng#11: add new typ…

9182cfb

…e mk_cpu_pkt to support both data and ctrl type from cpu in one packet

tancheng reviewed Jan 19, 2025

View reviewed changes

tancheng mentioned this pull request Jan 19, 2025

Initial commit for ctrl&data preloading. #69

Closed

[P2] Installation and Data Preloading Issue tancheng#11: rename vari…

6f5dde3

…ables to more meaningful

yuqisun mentioned this pull request Jan 20, 2025

[P3] Deliver addr2controller_vector via cpu_pkt #70

Open

yuqisun added 2 commits January 20, 2025 23:42

[P2] Installation and Data Preloading Issue tancheng#11: add new cmd…

c6c2747

… for const

Merge remote-tracking branch 'origin/master' into integrate_ConstMem

007e8f5

tancheng mentioned this pull request Feb 6, 2025

[feature] Move buffer at xbar inport from outport #78

Open

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yuqisun added 3 commits February 6, 2025 22:24

Extend mk_ring_across_tiles_pkt to have controller_id, data, data_addr

73c154f

s.controller.send_to_ctrl_ring_pkt -> s.controller.send_to_intra_cgra…

c7c0380

…_pkt

rename interfaces as per ControllerRTL

955033e

tancheng reviewed Feb 6, 2025

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rename prefix of mk_intra_cgra_pkt

7a8ca86

yuqisun added 2 commits February 8, 2025 12:37

feed pkt to ctrl/const mems

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feed pkt to ctrl/const mems

a8da0dc

Use ctrl mem and const mem in TileRTL

a592b11

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[P2] Installation and Data Preloading Issue #11: new data type #68

[P2] Installation and Data Preloading Issue #11: new data type #68

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[P2] Installation and Data Preloading Issue #11: new data type #68

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[P2] Installation and Data Preloading Issue #11: new data type #68

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