This repository contains my first probes with FPGA design using Verilog.

All exercuses are targeted to be run on very cheap FPGA development board Tang Nano 9K. This toy cost me 20 euro.

I don't take this activity very seriously, doing it just for fun, out of curiosity, to understand how these things work. Let's see how far I can get with this new hobby.

Links

• https://learn.lushaylabs.com
• https://www.fpga4fun.com
• https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-1-what-is-an-fpga/3ee5f6c8fa594161a655a9f960060893
• https://verilogguide.readthedocs.io/en/latest/index.html
• https://www.fpgadeveloper.com
• Zynq 7000 Tutorial:
  • https://www.beyond-circuits.com/wordpress/tutorial/
  • Official Xilinx Confluence: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/189530183/Zynq-7000

RISC-V on FPGA Tutorial https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/PIPELINE.md This is must have!!!

Future directions

Migen: A Python toolbox for building complex digital hardware https://github.com/m-labs/migen https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources https://www.controlpaths.com/2022/11/07/writing-verilog-code-using-python-with-migen/ Very nice slides and labs on Migen: https://github.com/litex-hub/fpga_101

RISC-V/SoC https://en.wikipedia.org/wiki/RISC-V https://github.com/BrunoLevy/learn-fpga https://github.com/YosysHQ/picorv32

AWS FPGA https://github.com/aws/aws-fpga

Litex Infrastructure to create FPGA Cores/SoCs Contains different ready to be reused cores like DRAM, Ethernet, SATA, PCI, different soft CPU cores... Supports mixing with direct HDL implementations and Migen https://github.com/enjoy-digital/litex/wiki