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RISC-V Simulator

The goal of this computer assignment is to create a (simple) C/C++ simulator for a (simple) RISC-V CPU.

This project is part of the coursework for the course ECE M116C - Computer Systems Architecture offered in Fall 2022 as part of my MS in ECE at UCLA. Kindly go through the Problem Statement.pdf for more details.

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A (simple) C/C++ simulator for a (simple) RISC-V CPU

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