Integrating vector and CHERI for RISC-V

[andresag01]

This PR has the following changes:

• Remove all outdated notes regarding CHERI and vector
• Remove pre-existing and incomplete vector instruction listings that were ifdef out
• Remove adoc defines to conditionally build the CHERI specification with/without vector
• Add a section describing how the RISC-V vector extension integrates with Zcheripurecap and Zcherihybrid:
  • Vector registers cannot hold capabilities with tag=1
  • Vector memory accesses are authorized by either ddc or a capability in a c register depending on the CHERI mode
  • Vector has all the usual memory access exceptions, but only body and active elements may give rise to out-of-bounds exceptions i.e. elements that are masked off, before vstart or after vl do not trap

Fixes #359