Add section on vector support #359
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Oct 9, 2024
This PR has the following changes:
* Remove all outdated notes regarding CHERI and vector
* Remove pre-existing and incomplete vector instruction listings that
were `ifdef` out
* Remove adoc defines to conditionally build the CHERI specification
with/without vector
* Add a section describing how the RISC-V vector extension integrates
with Zcheripurecap and Zcherihybrid:
* Vector registers cannot hold capabilities with tag=1
* Vector memory accesses are authorized by either `ddc` or a capability
in a **c** register depending on the CHERI mode
* Vector has all the usual memory access exceptions, but only _body_ and
_active_ elements may give rise to out-of-bounds exceptions i.e.
elements that are masked off, before vstart or after vl do not trap
Fixes riscv#359
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Signed-off-by: Tariq Kurd <tariqandlaura@gmail.com>
Co-authored-by: Tariq Kurd <tariq.kurd@codasip.com>
Co-authored-by: Tariq Kurd <tariqandlaura@gmail.com>
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The vector spec is simple "check every byte of every load/store access"
This needs adding to the doc.
The concept of adding tags into vector registers would be a future feature.
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