Verilog-A module

[medwatt]

I'm very new to using Qucs-S. I want to know how to include a verilog-a module, but I can't seem to find any resources. I'm familiar with using verilog-a via openvaf with ngspice, but not with Qucs-S.

[ra3xdh]

I have added support for the OpenVAF+Ngspice in the version 1.1.0. This feature is not well documented because of very low demand. You can find some notes on the Verilog-A model usage here #197 Also look at the MOS-AK presentation from 2014: https://mos-ak.org/venice_2014/publications/T_4_Brinson_MOS-AK_Venice_2014.pdf The procedure for the Qucs-S remains the same. The application will invoke OpenVAF instead of ADMS automatically if Ngspice is selected.

I have recently discovered that Verilog-A simulation is broken in the latest release v2.0.0. See #321. There is no workaround for this. You have to install v1.1.0 in a separate directory if the Verilog-A simulation is needed. I am planning to add the fix in the next release.

[medwatt]

Thanks for the reply. I came across that same thread and tried out the process described, but couldn't find a way to insert the symbol of the generated verilog-a file. To be more specific, I didn't see any tab for verilog-a user devices.

[ra3xdh]

I have fixed the #321 on the current branch. You may to compile Qucs-S from source to get access to Verilog-A simulation features.

[ra3xdh]

but couldn't find a way to insert the symbol of the generated verilog-a file

This is #321 It is fixed on current branch. You have either to build Qucs-S from source or install v1.1.0 For Windows I would recommend the second solution. Also please check the simulator settings, because these setting are incompatible between v1.1.0 and v2.0.0 Also check the openVAF compiler settings.

[ra3xdh]

You may also wait for the next release if the Verilog-A simulation is not urgent. I am planning to prepare the packages till the end of October.

[medwatt]

Actually, at the moment, I have a work around. I add the verilog-a file as a spice subcircuit.

[ra3xdh]

Yes, you may build the subcircuit and specify the OSDI modules using spiceinit #26

[medwatt]

Thanks, but this seems like an extra step that could be automated. How did verilog-a modules work in the past? For example, in Cadence Virtuoso, you would write the verilog-a file, save, get an automatic rectangular symbol with the ports, and then insert the symbol in the schematic. It was very easy. Also, you can easily use reuse verilog-a models between projects. So, you could have a library of verilog-a models and use them in different projects.

[ra3xdh]

this seems like an extra step that could be automated.

Yes, agreed with this. The Verilog-A support would benefit from redesing. The workflow with JSON files and module build/load was proposed by Qucs developers in 2014. I decided to reuse for Ngspice+OpenVAF and don't invent anything from scratch.

I have an idea to implement special Verilog-A file device that will look like as existing SPICE file device without JSON and manual build/load steps. The OpenVAF compiler should be invoked automatically if such device is presented in schematic. But don't expect the adding of this device in the near future because of very low demand. To be honestly, the Verilog-A simulation features are never used by 99% of Qucs-S users.

[medwatt]

Thanks once more for clarifying. Right now, I have a python script that automatically reads the verilog-a file, compiles it and generates a spice subcircuit that can be inserted. Not ideal but saves time doing the boring stuff.

I understand that verilog-a is very low priority, but it was the main reason I am trying qucs-s. I use LTSpice. It works quite well, but doesn't have support for verilog-a.

If I may also suggest something.

• Qucs-s is already very good, but for someone who is keyboard driven, I find it a too mouse-needy. For example, to get a component, one needs to open the components tab, go to the search box, type the name, move the mouse to the component, etc. This too much. For example, in LTspice, you have a key binding to open the component window, places you automatically in the search box where you can search for a component, and selects the first match. With just one key press, you have the component ready to be inserted.

• You can't rotate or flip a symbol before placing it on the schematic. This is also unnecessarily time consuming.

• No customizable shortcuts. For example, why is W used to wire and G used for ground. Maybe have R for resistor given how commonly used it is.

#!/usr/bin/env python

import sys
import os
import subprocess

# Specify the path to openvaf here
OPENVAF_PATH = "/home/user/applications/bin/openvaf"

def compile_veriloga(veriloga_file_path):
    module_name = ""
    nodes = []

    with open(veriloga_file_path, "r") as f:
        lines = f.readlines()
        for line in lines:
            if line.startswith("module "):
                words = line.split()
                module_name = words[1]
                nodes = line.split("(")[1].split(")")[0].split(", ")
                break

    if module_name == "" or len(nodes) == 0:
        print("Error: Could not parse Verilog-A file.")
        return

    # Compile using openvaf
    compile_command = f"{OPENVAF_PATH} {veriloga_file_path}"
    subprocess.run(compile_command, shell=True)

    # Create the output file
    output_filename = f"veriloga-{module_name}.sp"
    with open(output_filename, "w") as f:
        f.write(f"* Verilog-A Subcircuit\n\n")
        f.write(f".subckt veriloga-{module_name} {' '.join(nodes)}\n")
        f.write(f".model {module_name} {module_name}\n")
        f.write(f"NX1 {' '.join(nodes)} {module_name}\n")
        f.write(f".ends veriloga-{module_name}\n\n")
        f.write(f".control\n")
        f.write(f"pre_osdi {os.path.splitext(os.path.abspath(veriloga_file_path))[0]}.osdi\n")
        f.write(f".endc\n")

    print(f"Output file generated: {output_filename}")

if __name__ == "__main__":
    if len(sys.argv) < 2:
        print("Usage: compile_veriloga <path_to_veriloga_file>")
        sys.exit(1)

    veriloga_file_path = sys.argv[1]
    compile_veriloga(veriloga_file_path)