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Merge pull request #414 from os-fpga/axi_lite_ip_litex
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added setup_lec_sim command in axi_lite_ip_litex and axi_st_d256_gen2_only
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NadeemYaseen authored Oct 17, 2024
2 parents 61278c7 + c7116ca commit 708554b
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Showing 3 changed files with 13 additions and 5 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -259,6 +259,9 @@ parse_cga exit 1; }
else
echo ""
fi
echo "setup_lec_sim 10 2">>raptor_tcl.tcl
echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
echo "sta">>raptor_tcl.tcl
echo "power">>raptor_tcl.tcl
echo "bitstream $bitstream">>raptor_tcl.tcl
Expand All @@ -272,6 +275,8 @@ parse_cga exit 1; }
fi
fi

[ -f rtl/sim.v ] && sed -i -e "s|MEM_FILE_PATH|$PWD/rtl|g" rtl/sim.v

cd results_dir
echo "Device: $device">>results.log
echo "Strategy: $strategy">>results.log
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Expand Up @@ -2816,7 +2816,7 @@ end
// Port 0 | Read: Sync | Write: ---- |
reg [31:0] mem[0:5393];
initial begin
$readmemh("mem.init", mem);
$readmemh("MEM_FILE_PATH/mem.init", mem);
end
reg [31:0] mem_dat0;
always @(posedge sys_clk_1) begin
Expand All @@ -2831,7 +2831,7 @@ assign main_simsoc_dat_r = mem_dat0;
// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
reg [31:0] mem_1[0:874];
initial begin
$readmemh("mem_1.init", mem_1);
$readmemh("MEM_FILE_PATH/mem_1.init", mem_1);
end
reg [9:0] mem_1_adr0;
always @(posedge sys_clk_1) begin
Expand All @@ -2854,7 +2854,7 @@ assign main_ram_dat_r = mem_1[mem_1_adr0];
// Port 0 | Read: Sync | Write: ---- |
reg [7:0] mem_2[0:36];
initial begin
$readmemh("mem_2.init", mem_2);
$readmemh("MEM_FILE_PATH/mem_2.init", mem_2);
end
reg [5:0] mem_2_adr0;
always @(posedge sys_clk_1) begin
Expand All @@ -2869,8 +2869,8 @@ assign builder_csr_bankarray_dat_r = mem_2[mem_2_adr0];
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage[0:15];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
reg [9:0] storage_dat0=10'd0;
reg [9:0] storage_dat1=10'd0;
always @(posedge sys_clk_1) begin
if (main_uart_tx_fifo_wrport_we)
storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w;
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Original file line number Diff line number Diff line change
Expand Up @@ -275,6 +275,9 @@ parse_cga exit 1; }
else
echo ""
fi
echo "setup_lec_sim 10 2">>raptor_tcl.tcl
echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
echo "sta">>raptor_tcl.tcl
echo "power">>raptor_tcl.tcl
echo "bitstream $bitstream">>raptor_tcl.tcl
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