Merge pull request #413 from os-fpga/library

updated design library rtl
os-fpga · Oct 16, 2024 · 61278c7 · 61278c7
2 parents 20d92aa + 6f38f31
commit 61278c7
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Showing 13 changed files with 98 additions and 100 deletions.
diff --git a/random_test_generator_v1/Design_Library/d_latch_top/rtl/d_latch_top.v b/random_test_generator_v1/Design_Library/d_latch_top/rtl/d_latch_top.v
@@ -7,7 +7,7 @@ module d_latch_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     reg enable;
     wire [WIDTH-1:0] d_out;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             enable <= 0;
         else

diff --git a/random_test_generator_v1/Design_Library/decoder_top/rtl/decoder_top.v b/random_test_generator_v1/Design_Library/decoder_top/rtl/decoder_top.v
@@ -1,3 +1,5 @@
+`timescale 1ns / 1ps
+
 module decoder_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     input clk;
     input rst;
@@ -7,7 +9,7 @@ module decoder_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     reg enable;
     wire [WIDTH-1:0] d_out;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             enable <= 0;
         else
@@ -29,7 +31,7 @@ module decoder #(parameter WIDTH=32)(
     );
     reg [WIDTH-1:0 ] data_out_w;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else
@@ -40,16 +42,17 @@ module decoder #(parameter WIDTH=32)(
     end
 
     always @ (data_in) begin
-        case(data_in) // synopsys full_case
-            32'b00000000000000000000000000000000: data_out_w = 32'd11111110;
-            32'b00000000000000000000000000000001: data_out_w = 32'd11111101;
-            32'b00000000000000000000000000000010: data_out_w = 32'd11111011;
-            32'b00000000000000000000000000000011: data_out_w = 32'd11110111;
-            32'b00000000000000000000000000000100: data_out_w = 32'd11101111;
-            32'b00000000000000000000000000000101: data_out_w = 32'd11011111;
-            32'b00000000000000000000000000000110: data_out_w = 32'd10111111;
-            32'b00000000000000000000000000000111: data_out_w = 32'd01111111;
- 	 	 	default: data_out_w = 32'd11111111;
+        case(data_in[2:0]) // synopsys full_case
+            3'b000: data_out_w = 32'b10111111111110111111111111111110;
+            3'b001: data_out_w = 32'b11011111111110111111111111111101;
+            3'b010: data_out_w = 32'b11101111111110111111111111111011;
+            3'b011: data_out_w = 32'b11110111111110111111111111110111;
+            3'b100: data_out_w = 32'b11111011111110111111111111101111;
+            3'b101: data_out_w = 32'b11111101111110111111111111011111;
+            3'b110: data_out_w = 32'b11111110111110111111111110111111;
+            3'b111: data_out_w = 32'b11111111011110111111111101111111;
+
+            default: data_out_w = 32'b11111111111111111111111111111111;
          endcase
     end
 

diff --git a/random_test_generator_v1/Design_Library/encoder/rtl/encoder.v b/random_test_generator_v1/Design_Library/encoder/rtl/encoder.v
@@ -8,7 +8,7 @@ output reg [WIDTH-1:0] data_out
 
 reg [WIDTH-1:0 ] data_out_wire;
 
-always@(posedge clk)
+always@(posedge clk or posedge rst)
 begin 
 if(rst)
 data_out<=0;
@@ -35,7 +35,7 @@ else
 if (data_in==32'd7000)
 data_out_wire=~32'd4000;
 else
-data_out_wire=0;
+data_out_wire=32'h6789ABCD;
 end
 
 

diff --git a/random_test_generator_v1/Design_Library/full_adder_top/rtl/full_adder_top.v b/random_test_generator_v1/Design_Library/full_adder_top/rtl/full_adder_top.v
@@ -9,11 +9,11 @@ module full_adder_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     wire cout;
 
 
-    always @ (posedge clk) begin
-        if (!rst)
-            cin <= 1;
-        else
+    always @ (posedge clk or posedge rst) begin
+        if (rst)
             cin <= 0;
+        else
+            cin <= 1;
     end
 
     full_adder #(.WIDTH(WIDTH)) full_adder_inst (.clk(clk),.rst(rst),.data_in(data_in),.data_out(d_out),.cin(cin),.cout(cout));
@@ -36,7 +36,7 @@ module full_adder #(parameter WIDTH=32)(
     reg [15:0] a,b;
     reg c;
 
-    always @(posedge clk) begin
+    always @(posedge clk or posedge rst) begin
         if (rst) begin
             a<=0;
             b<=0;
@@ -47,8 +47,7 @@ module full_adder #(parameter WIDTH=32)(
             a <= data_in[15:0];
             b <= data_in[31:16];
             c <= cin;
-            data_out <= a^b^c;
-            cout <= (a & b)|(c & b)|(a & c);
+            {cout , data_out} <= a+b+c;
         end
 
     end

diff --git a/random_test_generator_v1/Design_Library/invertion/rtl/invertion.v b/random_test_generator_v1/Design_Library/invertion/rtl/invertion.v
@@ -1,33 +1,26 @@
-module invertion
-#(parameter WIDTH=32) 
-(
-input clk,
-input rst,
-input [WIDTH-1:0] data_in,
-output [WIDTH-1:0] data_out);
+module invertion #(parameter WIDTH = 32)(
+    input wire clk,
+    input wire rst,
+    input wire [WIDTH-1:0] data_in,
+    output reg [WIDTH-1:0] data_out
+);
 
-reg [7:0] data_out_reg;
-wire [7:0] data_out_wire;
+    wire [7:0] bitwise_not_and_or;
+    wire [7:0] bitwise_xor;
+    wire [15:0] conditional_invert;
 
-assign data_out_wire[7:0] = ((~data_in[7:0]) | (~data_in[15:8]));
+    assign bitwise_not_and_or = (~data_in[7:0]) | (~data_in[15:8]);
 
-always@(posedge clk)
-begin
-if (rst)
-begin 
-data_out_reg[7:0]<=0;
-end
-else 
-begin 
-data_out_reg[7:0]<= data_in[31:24] ^ data_in[23:16];
+    assign bitwise_xor = data_in[31:24] ^ data_in[23:16];
 
-end
-end
-
-assign data_out[31:16] = (data_in[31:16] == data_in[15:0])? ~data_in[15:0]: ^data_in[31:16];
-
-assign data_out[15:0] = {data_out_reg,data_out_wire};
+    assign conditional_invert = (data_in[31:16] == data_in[15:0]) ? data_in[15:0] : ~data_in[31:16];
 
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            data_out <= 0;
+        end else begin
+            data_out <= {conditional_invert, bitwise_xor, bitwise_not_and_or};
+        end
+    end
 
 endmodule
-
diff --git a/random_test_generator_v1/Design_Library/large_adder/rtl/large_adder.v b/random_test_generator_v1/Design_Library/large_adder/rtl/large_adder.v
@@ -10,7 +10,7 @@ reg [WIDTH-1:0] add_out_reg_0;
 reg [WIDTH-1:0] add_out_reg_1;
 reg [WIDTH-1:0] add_out_reg_2;
 
-always@(posedge clk)
+always@(posedge clk or posedge rst)
 begin
 if(rst)
 begin
@@ -25,7 +25,7 @@ add_out_reg_1<=(data_in[WIDTH-1:WIDTH-16] - data_in[WIDTH-16-1:0]);
 add_out_reg_2<=(data_in[WIDTH-1:WIDTH-16] + data_in[WIDTH-16-1:0]);
 end
 end
-assign data_out = add_out_reg_0 * add_out_reg_1 + add_out_reg_2;
+assign data_out = add_out_reg_0 + add_out_reg_1 * add_out_reg_2;
 
 endmodule
 

diff --git a/random_test_generator_v1/Design_Library/large_mux/rtl/large_mux.v b/random_test_generator_v1/Design_Library/large_mux/rtl/large_mux.v
@@ -1,42 +1,48 @@
 module large_mux 
 #(parameter WIDTH=32)
 (
-input clk,
-input rst,
-input [WIDTH-1:0] data_in,
-output reg [WIDTH-1:0] data_out);
-
-//reg [WIDTH-1:0] data_out = 32'd0;
-
-always@(data_in) begin 
-casex(data_in)
-32'hxxxxxxx0:data_out[31:0] = {24'b0,data_in[7:0]};
-32'hxxxxxxx1:data_out[31:0] = {16'b0,data_in[15:8],8'b0};
-32'hxxxxxxx2:data_out[31:0] = {8'b0,data_in[23:16],16'b0};
-32'hxxxxxxx3:data_out[31:0] = {data_in[31:24],24'b0};
-
-32'hxxxxxx0x:data_out[31:0] = {16'b0,data_in[15:8],8'b0};
-32'hxxxxxx1x:data_out[31:0] = {8'b0,data_in[23:16],16'b0};
-32'hxxxxxx2x:data_out[31:0] = {data_in[31:24],24'b0};
-32'hxxxxxx3x:data_out[31:0] = {24'b0,data_in[7:0]};
-
-32'hxxxxx0xx:data_out[31:0] = {8'b0,data_in[23:16],16'b0};
-32'hxxxxx1xx:data_out[31:0] = {data_in[31:24],24'b0};
-32'hxxxxx2xx:data_out[31:0] = {24'b0,data_in[7:0]};
-32'hxxxxx3xx:data_out[31:0] = {16'b0,data_in[15:8],8'b0};
-
-32'hxxxx0xxx:data_out[31:0] = {data_in[31:24],24'b0};
-32'hxxxx1xxx:data_out[31:0] = {24'b0,data_in[7:0]};
-32'hxxxx2xxx:data_out[31:0] = {16'b0,data_in[15:8],8'b0};
-32'hxxxx3xxx:data_out[31:0] = {8'b0,data_in[23:16],16'b0};
-
-default: data_out[31:0]= 32'd0;
-endcase
+    input clk,
+    input rst,
+    input [WIDTH-1:0] data_in,
+    output reg [WIDTH-1:0] data_out
+);
+reg [WIDTH-1:0] data_out_reg;
+
+// Output logic: either reset or update data_out from data_out
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        data_out_reg <= 0;
+    else
+        case(data_in[3:0])  // Focus on the lower 4 bits
+        4'b0000: data_out_reg <= {24'b0, data_in[7:0]};
+        4'b0001: data_out_reg <= {16'b0, data_in[15:8], 8'b0};
+        4'b0010: data_out_reg <= {8'b0, data_in[23:16], 16'b0};
+        4'b0011: data_out_reg <= {data_in[31:24], 24'b0};
+
+        4'b0100: data_out_reg <= {16'b0, data_in[15:8], 8'b0};
+        4'b0101: data_out_reg <= {8'b0, data_in[23:16], 16'b0};
+        4'b0110: data_out_reg <= {data_in[31:24], 24'b0};
+        4'b0111: data_out_reg <= {24'b0, data_in[7:0]};
+
+        4'b1000: data_out_reg <= {8'b0, data_in[23:16], 16'b0};
+        4'b1001: data_out_reg <= {data_in[31:24], 24'b0};
+        4'b1010: data_out_reg <= {24'b0, data_in[7:0]};
+        4'b1011: data_out_reg <= {16'b0, data_in[15:8], 8'b0};
+
+        4'b1100: data_out_reg <= {data_in[31:24], 24'b0};
+        4'b1101: data_out_reg <= {24'b0, data_in[7:0]};
+        4'b1110: data_out_reg <= {16'b0, data_in[15:8], 8'b0};
+        4'b1111: data_out_reg <= {8'b0, data_in[23:16], 16'b0};
+
+        default: data_out_reg <= 32'd0;
+        endcase
 end
-endmodule
-
-
-
-
 
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        data_out <= 0;
+    else
+        data_out <= data_out_reg;
+end
 
+endmodule
diff --git a/random_test_generator_v1/Design_Library/memory_cntrl/rtl/memory_cntrl.v b/random_test_generator_v1/Design_Library/memory_cntrl/rtl/memory_cntrl.v
@@ -27,15 +27,14 @@ always@(posedge clk)
          rd_addr<=0;
          wr_en<=0;
          rd_en<=0;
+         wr_data_mem<=0;
       end
       else 
       case(state) //synopsys full_case
          s0: 
             begin
-               wr_data_mem<=0;
                if (wr_addr==10'b1111111111) begin
                   state<=s1;
-                  wr_addr<=1;
                   wr_en<=0;
                   reset_mem<=0;  
                end
@@ -44,15 +43,13 @@ always@(posedge clk)
                  state<=s0;
                  wr_addr<=wr_addr+1;
                  wr_en<=1;
+                 wr_data_mem<=data_in;
                end
             end
          s1:
             begin
-               wr_data_mem<=data_in;
                rd_en<=1;
                rd_addr<=rd_addr+1;
-               // wr_en<=1;
-               // wr_addr<=wr_addr+1;
                state<=s1;
             end
          default: state<=s0;
@@ -99,7 +96,7 @@ always@(posedge clk) begin
       end
    end
 
-always@(posedge clk) begin
+always@(posedge clk or posedge rst) begin
    if(rst) begin 
       rd_data_out<=0; end
    else begin

diff --git a/random_test_generator_v1/Design_Library/mod_n_counter/rtl/mod_n_counter.v b/random_test_generator_v1/Design_Library/mod_n_counter/rtl/mod_n_counter.v
@@ -5,7 +5,7 @@ module mod_n_counter #(parameter N=256, parameter WIDTH = 32)(
     output reg [WIDTH-1:0] data_out
     );
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else begin

diff --git a/random_test_generator_v1/Design_Library/paritygenerator_top/rtl/paritygenerator_top.v b/random_test_generator_v1/Design_Library/paritygenerator_top/rtl/paritygenerator_top.v
@@ -9,7 +9,7 @@ module paritygenerator_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     wire parity;
 
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else
@@ -33,7 +33,7 @@ module paritygenerator #(parameter WIDTH=32)(
 
     reg [WIDTH-1:0] data_out_reg;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else

diff --git a/random_test_generator_v1/Design_Library/register/rtl/register.v b/random_test_generator_v1/Design_Library/register/rtl/register.v
@@ -7,7 +7,7 @@ input [WIDTH-1:0] data_in,
 output reg [WIDTH-1:0] data_out);
 
 
-always@(posedge clk)
+always@(posedge clk or posedge rst)
 begin 
 if(rst)
 data_out<=0;

diff --git a/random_test_generator_v1/Design_Library/shift_reg_top/rtl/shift_reg_top.v b/random_test_generator_v1/Design_Library/shift_reg_top/rtl/shift_reg_top.v
@@ -7,7 +7,7 @@ module shift_reg_top #(parameter WIDTH=32) (clk,rst,data_in,data_out);
     reg enable;
     wire [WIDTH-1:0] d_out;
 
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             enable <= 0;
         else
@@ -29,12 +29,12 @@ module shift_reg #(parameter WIDTH=32) (
     );
 //    wire d;
 //    assign d=1;
-    always @ (posedge clk) begin
+    always @ (posedge clk or posedge rst) begin
         if (rst)
             data_out <= 0;
         else begin
             if (en)
-                data_out <= {data_out[WIDTH-1:0],data_in[WIDTH-16:0]};
+                data_out <= {data_out[WIDTH-17:0],data_in[WIDTH-17:0]};
             else
                 data_out <= data_in;
         end

diff --git a/random_test_generator_v1/Design_Library/single_port_ram_top/rtl/single_port_ram_top.v b/random_test_generator_v1/Design_Library/single_port_ram_top/rtl/single_port_ram_top.v
@@ -8,7 +8,7 @@ module single_port_ram_top #(parameter WIDTH = 32)(
 	wire [5:0] addr = data_in[6:1];
 	wire we = data_in[0];
 
-	always @ (posedge clk) begin
+	always @ (posedge clk or posedge rst) begin
 	if (rst)
 		data_out <= 0;
 	else