add param & fix install path

gnuradio · Aug 20, 2019 · 469510e · 469510e
1 parent e610f49
commit 469510e
Show file tree

Hide file tree

Showing 10 changed files with 55 additions and 22 deletions.
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -202,6 +202,7 @@ add_subdirectory(python)
 add_subdirectory(grc)
 add_subdirectory(apps)
 add_subdirectory(docs)
+add_subdirectory(templates)
 
 ########################################################################
 # Install cmake search helper for this library

diff --git a/grc/verilog_verilog_axi_ii.xml b/grc/verilog_verilog_axi_ii.xml
@@ -3,7 +3,7 @@
   <key>verilog_axi_ii</key>
   <category>[Verilog]</category>
   <import>import verilog</import>
-  <make>verilog.verilog_axi_$(type.fcn)($file, $overwrite, $IO_ratio, $verilator_options, $skip_output_items)</make>
+  <make>verilog.verilog_axi_$(type.fcn)($file, $overwrite, $IO_ratio, $verilator_options, $module_flag, $skip_output_items)</make>
   <param>
     <name>Verilog File</name>
     <key>file</key>
@@ -46,6 +46,12 @@
     <value/>
     <type>string</type>
   </param>
+  <param>
+    <name>Module Flag</name>
+    <key>module_flag</key>
+    <value>0</value>
+    <type>int</type>
+  </param>
   <param>
     <name>Skip Output</name>
     <key>skip_output_items</key>

diff --git a/grc/verilog_verilog_axi_ii.yml b/grc/verilog_verilog_axi_ii.yml
@@ -27,6 +27,10 @@ parameters:
     label: Verilator Options
     dtype: string
     default: '""'
+-   id: module_flag
+    label: Module Flag
+    dtype: int
+    default: '0'
 -   id: skip_output_items
     label: Skip Output
     dtype: int
@@ -42,7 +46,7 @@ outputs:
 
 templates:
     imports: import verilog
-    make: verilog.verilog_verilog_axi_${type.fcn}(${file}, ${overwrite}, ${IO_ratio}, ${verilator_options}, ${skip_output_items})
+    make: verilog.verilog_verilog_axi_${type.fcn}(${file}, ${overwrite}, ${IO_ratio}, ${verilator_options}, ${module_flag}, ${skip_output_items})
 
 
 file_format: 1
diff --git a/include/verilog/verilog_axi_ii.h b/include/verilog/verilog_axi_ii.h
@@ -47,7 +47,8 @@ namespace gr {
        * creating new instances.
        */
       static sptr make(const char *filename, bool overwrite, float IO_ratio,
-                       const char *verilator_options, unsigned int skip_output_items);
+                       const char *verilator_options, unsigned int module_flag,
+                       unsigned int skip_output_items);
     };
 
   } // namespace verilog

diff --git a/lib/constants.cc.in b/lib/constants.cc.in
@@ -25,7 +25,7 @@ namespace gr {
   namespace verilog {
     const std::string
     datadir() {
-      return "@GR_PKG_DATA_DIR@";
+      return "@CMAKE_INSTALL_PREFIX@/@GR_PKG_DATA_DIR@/templates/";
     }
 
     std::string

diff --git a/lib/verilog_axi_ii_impl.cc b/lib/verilog_axi_ii_impl.cc
@@ -52,18 +52,19 @@ namespace gr {
 
     verilog_axi_ii::sptr
     verilog_axi_ii::make(const char *filename, bool overwrite, float IO_ratio,
-                         const char *verilator_options, unsigned int skip_output_items)
+                         const char *verilator_options, unsigned int module_flag, unsigned int skip_output_items)
     {
       return gnuradio::get_initial_sptr
         (new verilog_axi_ii_impl(filename, overwrite, IO_ratio,
-                                 verilator_options, skip_output_items));
+                                 verilator_options, module_flag, skip_output_items));
     }
 
     /*
      * The private constructor
      */
     verilog_axi_ii_impl::verilog_axi_ii_impl(const char *filename, bool overwrite, float IO_ratio,
-                                             const char *verilator_options, unsigned int skip_output_items)
+                                             const char *verilator_options, unsigned int module_flag,
+                                             unsigned int skip_output_items)
       : gr::block("verilog_axi_ii",
               gr::io_signature::make(1, 1, sizeof(ITYPE)),
               gr::io_signature::make(1, 1, sizeof(OTYPE)))
@@ -79,18 +80,23 @@ namespace gr {
       this->verilog_module_path = filename_temp.substr(0, filename_pos + 1);
 
       // Test access
-      this->test_access(filename, "can't access verilog file");
+      this->test_access(filename,
+                        (std::string("\ncan't access verilog file in: ") +
+                         this->verilog_module_path).c_str());
 
       /* Initialize makefile_template_path and cpp_template_path */
       this->makefile_template_path = MAKEFILE_TEMPLATE_PATH;
       this->cpp_template_path = CPP_TEMPLATE_PATH;
       // Test access
       this->test_access((this->makefile_template_path + AXI_MODULE_CL_MAKEFILE).c_str(),
-                        "can't access makefile template");
+                        (std::string("\ncan't access makefile template in: ") +
+                         this->makefile_template_path).c_str());
       this->test_access((this->cpp_template_path + CPP_TEMPLATE_NAME).c_str(),
-                         "can't access cpp template");
+                        (std::string("\ncan't access cpp template in: ") +
+                         this->cpp_template_path).c_str());
       this->test_access((this->cpp_template_path + HEADER_TEMPLATE_NAME).c_str(),
-                         "can't access header template");
+                        (std::string("\ncan't access header template in: ") +
+                         this->cpp_template_path).c_str());
 
       // Reset the initial time
       this->main_time = 0;
@@ -107,6 +113,9 @@ namespace gr {
       // Set verilator options
       this->verilator_options = std::string(verilator_options);
 
+      // Set module_flag
+      this->module_flag = module_flag;
+
       /* Call Verilator (Makefile) to generate the cpp code */
       // There will be a Shell_cmd object created in the function to
       // run configure.sh
@@ -220,7 +229,7 @@ namespace gr {
         }
 
         axi_init();
-        axi_reset(this->skip_output_items);
+        axi_reset(this->module_flag);
 
         this->sim =
             (Simulation_func)this->verilog_module_so.find_func("AXI_async_transfer_ii");
@@ -250,11 +259,16 @@ namespace gr {
           throw;
         }
 
+        // input
         if (status_code & (1 << 1)) {
           ++input_i;
         }
+        // output
         if (status_code & 1) {
-          ++output_i;
+          if (this->skip_output_items > 0)
+            --this->skip_output_items;
+          else
+            ++output_i;
         }
       }
 
@@ -351,6 +365,9 @@ namespace gr {
         if (cl_err_code == _EXIT_FAILURE) {
           throw std::runtime_error("Shell_cmd execute error");
         }
+
+        // Output the message
+        // bash.print_msg(std::cout);
       }
       catch (...) {
         bash.print_msg(std::cerr);

diff --git a/lib/verilog_axi_ii_impl.h b/lib/verilog_axi_ii_impl.h
@@ -75,6 +75,10 @@ namespace gr {
 
       std::string verilator_options;
 
+      // the parameter send to the template cpp code in function reset(unsiged int)
+      // user can make use of it
+      unsigned int module_flag;
+
       /* gr::verilog::verilog_axi_ii private member variables  */
 
 
@@ -114,7 +118,8 @@ namespace gr {
 
      public:
       verilog_axi_ii_impl(const char *filename, bool overwrite, float IO_ratio,
-                          const char *verilator_options, unsigned int skip_output_items);
+                          const char *verilator_options, unsigned int module_flag,
+                          unsigned int skip_output_items);
       ~verilog_axi_ii_impl();
 
       // Where all the action really happens

diff --git a/python/qa_verilog_axi_ii.py b/python/qa_verilog_axi_ii.py
@@ -36,7 +36,7 @@ def test_001_t (self):
         src_data = (1, 3, 5, 9, 10, 12, 17, 19, 21, 12, 45, 29)
         expected_result = (1, 3, 5, 9, 10, 12, 17, 19, 21, 12, 45, 29)
         src = blocks.vector_source_i(src_data)
-        vl = verilog.verilog_axi_ii("/home/bowen/Downloads/temp/saxi_passthru.v", True, 1.0, "-Wall", 0)
+        vl = verilog.verilog_axi_ii("/home/bowen/Downloads/temp/saxi_passthru.v", True, 1.0, "-Wall", 0, 0)
         dst = blocks.vector_sink_i()
 
         self.tb.connect(src, vl)
@@ -53,7 +53,7 @@ def test_002_t (self):
         src_data = (1, 3, 5, 9, 10, 12, 17, 19, 21)
         expected_result = (2, 6, 10, 18, 20, 24, 34, 38, 42)
         src = blocks.vector_source_i(src_data)
-        vl = verilog.verilog_axi_ii("/home/bowen/Downloads/double/double_axi.v", True, 1.0, "", 0)
+        vl = verilog.verilog_axi_ii("/home/bowen/Downloads/double/double_axi.v", True, 1.0, "", 0, 0)
         dst = blocks.vector_sink_i()
 
         self.tb.connect(src, vl)

diff --git a/templates/axi_module.cpp b/templates/axi_module.cpp
@@ -39,15 +39,14 @@ void AXI_init()
   char** argv = NULL;
   Verilated::commandArgs(argc, argv);
 
+  skip_output_items = SKIP_OUTPUT_ITEMS;
+
   if (NULL == top)
     top = new Vaxi_module;
 }
 
-void AXI_reset(unsigned int skip_n)
-{
-  skip_output_items = skip_n > (unsigned int)SKIP_OUTPUT_ITEMS ? 
-                      skip_n : (unsigned int)SKIP_OUTPUT_ITEMS;
-
+void AXI_reset(unsigned int module_flag)
+{ 
   top->ACLK = 0;
   top->ARESETn = 0;
   top->eval();

diff --git a/templates/axi_module.h b/templates/axi_module.h
@@ -12,7 +12,7 @@ static Vaxi_module* top = NULL;
 
 void AXI_init();
 
-void AXI_reset(unsigned int skip_n);
+void AXI_reset(unsigned int module_flag);
 
 void AXI_sync_transfer_ii(const unsigned int &gr_input,
                           unsigned int &gr_output,