GUI & bug fix

gnuradio · Aug 19, 2019 · e610f49 · e610f49
1 parent 3cfa541
commit e610f49
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Showing 5 changed files with 104 additions and 30 deletions.
diff --git a/grc/CMakeLists.txt b/grc/CMakeLists.txt
@@ -19,4 +19,5 @@
 
 install(FILES
     verilog_verilog_axi_ii.xml DESTINATION share/gnuradio/grc/blocks
+    # verilog_verilog_axi_ii.yml DESTINATION share/gnuradio/grc/blocks
 )
diff --git a/grc/verilog_verilog_axi_ii.xml b/grc/verilog_verilog_axi_ii.xml
@@ -1,38 +1,63 @@
-<?xml version="1.0"?>
 <block>
-  <name>verilog_axi_ii</name>
-  <key>verilog_verilog_axi_ii</key>
-  <category>[verilog]</category>
+  <name>Verilog AXI</name>
+  <key>verilog_axi_ii</key>
+  <category>[Verilog]</category>
   <import>import verilog</import>
-  <make>verilog.verilog_axi_ii($*filename)</make>
-  <!-- Make one 'param' node for every Parameter you want settable from the GUI.
-       Sub-nodes:
-       * name
-       * key (makes the value accessible as $keyname, e.g. in the make node)
-       * type -->
+  <make>verilog.verilog_axi_$(type.fcn)($file, $overwrite, $IO_ratio, $verilator_options, $skip_output_items)</make>
   <param>
-    <name>...</name>
-    <key>...</key>
-    <type>...</type>
+    <name>Verilog File</name>
+    <key>file</key>
+    <value/>
+    <type>file_open</type>
+  </param>
+  <param>
+    <name>IO Type</name>
+    <key>type</key>
+    <type>enum</type>
+    <option>
+      <name>Int</name>
+      <key>int</key>
+      <opt>fcn:ii</opt>
+    </option>
+  </param>
+  <param>
+    <name>Overwrite</name>
+    <key>overwrite</key>
+    <value>False</value>
+    <type>enum</type>
+    <option>
+      <name>Yes</name>
+      <key>True</key>
+    </option>
+    <option>
+      <name>No</name>
+      <key>False</key>
+    </option>
+  </param>
+  <param>
+    <name>IO Ratio</name>
+    <key>IO_ratio</key>
+    <value>1.0</value>
+    <type>float</type>
+  </param>
+  <param>
+    <name>Verilator Options</name>
+    <key>verilator_options</key>
+    <value/>
+    <type>string</type>
+  </param>
+  <param>
+    <name>Skip Output</name>
+    <key>skip_output_items</key>
+    <value>0</value>
+    <type>int</type>
   </param>
-
-  <!-- Make one 'sink' node per input. Sub-nodes:
-       * name (an identifier for the GUI)
-       * type
-       * vlen
-       * optional (set to 1 for optional inputs) -->
   <sink>
     <name>in</name>
-    <type><!-- e.g. int, float, complex, byte, short, xxx_vector, ...--></type>
+    <type>$type</type>
   </sink>
-
-  <!-- Make one 'source' node per output. Sub-nodes:
-       * name (an identifier for the GUI)
-       * type
-       * vlen
-       * optional (set to 1 for optional inputs) -->
   <source>
     <name>out</name>
-    <type><!-- e.g. int, float, complex, byte, short, xxx_vector, ...--></type>
+    <type>$type</type>
   </source>
 </block>
diff --git a/grc/verilog_verilog_axi_ii.yml b/grc/verilog_verilog_axi_ii.yml
@@ -0,0 +1,48 @@
+id: verilog_verilog_axi_xx
+label: Verilog AXI
+flags: [ python, cpp ]
+
+parameters:
+-   id: file
+    label: Verilog File
+    dtype: file_open
+-   id: type
+    label: IO Type
+    dtype: enum
+    options: [complex, float, int, short]
+    option_attributes:
+        fcn: [cc, ff, ii, ss]
+    hide: part
+-   id: overwrite
+    label: Overwrite
+    dtype: enum
+    default: 'False'
+    options: ['True', 'False']
+    option_labels: ['Yes', 'No']
+-   id: IO_ratio
+    label: IO Ratio
+    dtype: real
+    default: '1.0'
+-   id: verilator_options
+    label: Verilator Options
+    dtype: string
+    default: '""'
+-   id: skip_output_items
+    label: Skip Output
+    dtype: int
+    default: '0'
+
+inputs:
+-   domain: stream
+    dtype: ${ type }
+
+outputs:
+-   domain: stream
+    dtype: ${ type }
+
+templates:
+    imports: import verilog
+    make: verilog.verilog_verilog_axi_${type.fcn}(${file}, ${overwrite}, ${IO_ratio}, ${verilator_options}, ${skip_output_items})
+
+
+file_format: 1
diff --git a/lib/verilog_axi_ii_impl.cc b/lib/verilog_axi_ii_impl.cc
@@ -105,7 +105,7 @@ namespace gr {
       this->IO_ratio = IO_ratio;
 
       // Set verilator options
-      this->verilator_options = verilator_options;
+      this->verilator_options = std::string(verilator_options);
 
       /* Call Verilator (Makefile) to generate the cpp code */
       // There will be a Shell_cmd object created in the function to

diff --git a/templates/axi_module_cl.mk b/templates/axi_module_cl.mk
@@ -27,13 +27,13 @@ endif
 USER_VL_FILENAME =
 USER_CPP_FILENAME =
 M_DIR =
-VERILATEOR_OPTIONS =
+VERILATOR_OPTIONS =
 
 VM_PREFIX = Vaxi_module
 
 VERILATOR_FLAGS =
 # Options from block
-VERILATOR_FLAGS += $(VERILATEOR_OPTIONS)
+VERILATOR_FLAGS += $(VERILATOR_OPTIONS)
 # Generate -fPIC code for shared library
 VERILATOR_FLAGS += -CFLAGS -fPIC
 # Change the module to fixed name