add examples

examples/double/double.v

@@ -0,0 +1,10 @@
+module double(
+  input         clock,
+  input         reset,
+  input  [31:0] io_in,
+  output [31:0] io_out
+);
+  // wire [32:0] temp;
+  // assign temp = 32'b1 + io_in;
+  assign io_out = io_in << 1;//temp[31:0];
+endmodule

examples/double/double_axi.v

@@ -0,0 +1,22 @@
+module double_axi(
+  input         ACLK,
+  input         ARESETn,
+  output        TREADY_IN,
+  input         TVALID_IN,
+  input  [31:0] TDATA_IN,
+  input         TREADY_OUT,
+  output        TVALID_OUT,
+  output [31:0] TDATA_OUT
+);
+
+double DUT(
+  .clock(ACLK),
+  .reset(ARESETn),
+  .io_in(TDATA_IN),
+  .io_out(TDATA_OUT)
+);
+
+assign TREADY_IN  = 1'b1;
+assign TVALID_OUT = 1'b1;
+
+endmodule