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Revert load instructions with reserved bits[14:12] = 111 #109

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Jan 9, 2025
Merged

Revert load instructions with reserved bits[14:12] = 111 #109

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d43f40a
Revert load instructions with reserved bits[14:12] = 111
mininny Dec 16, 2024
f35812f
Add solidity test for revert case
mininny Dec 16, 2024
66d0362
Merge branch 'master' into feature/mininny/audit-5
mininny Jan 8, 2025
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6 changes: 6 additions & 0 deletions rvgo/fast/vm.go
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Original file line number Diff line number Diff line change
Expand Up @@ -587,6 +587,12 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
switch opcode {
case 0x03: // 000_0011: memory loading
// LB, LH, LW, LD, LBU, LHU, LWU

// bits[14:12] set to 111 are reserved
if eq64(funct3, toU64(0x7)) != 0 {
revertWithCode(riscv.ErrInvalidSyscall, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
}

imm := parseImmTypeI(instr)
signed := iszero64(and64(funct3, toU64(4))) // 4 = 100 -> bitflag
size := shl64(and64(funct3, toU64(3)), toU64(1)) // 3 = 11 -> 1, 2, 4, 8 bytes size
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6 changes: 6 additions & 0 deletions rvgo/slow/vm.go
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Expand Up @@ -760,6 +760,12 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
switch opcode.val() {
case 0x03: // 000_0011: memory loading
// LB, LH, LW, LD, LBU, LHU, LWU

// bits[14:12] set to 111 are reserved
if eq64(funct3, toU64(0x7)) != (U64{}) {
revertWithCode(riscv.ErrInvalidSyscall, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
}

imm := parseImmTypeI(instr)
signed := iszero64(and64(funct3, toU64(4))) // 4 = 100 -> bitflag
size := shl64(and64(funct3, toU64(3)), toU64(1)) // 3 = 11 -> 1, 2, 4, 8 bytes size
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4 changes: 4 additions & 0 deletions rvsol/src/RISCV.sol
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Expand Up @@ -1147,6 +1147,10 @@ contract RISCV is IBigStepper {
let pc_ := _pc
// 000_0011: memory loading
// LB, LH, LW, LD, LBU, LHU, LWU

// bits[14:12] set to 111 are reserved
if eq64(funct3, toU64(0x7)) { revertWithCode(0xf001ca11) }

let imm := parseImmTypeI(instr)
let signed := iszero64(and64(funct3, toU64(4))) // 4 = 100 -> bitflag
let size := shl64(and64(funct3, toU64(3)), toU64(1)) // 3 = 11 -> 1, 2, 4, 8 bytes size
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12 changes: 12 additions & 0 deletions rvsol/test/RISCV.t.sol
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Expand Up @@ -2460,6 +2460,18 @@ contract RISCV_Test is CommonTest {
riscv.step(encodedState, proof, 0);
}

function test_reserved_load_instruction() public {
bytes32 value = hex"61fb11d66dcc9d48";
uint16 offset = 0x6bf;
uint64 addr = 0xd34d + offset;
uint32 insn = encodeIType(0x3, 21, 0x7, 4, offset); // lhu x21, funct 0x7, offset(x4)
(State memory state, bytes memory proof) = constructRISCVState(0, insn, addr, value);
state.registers[4] = 0xd34d;
bytes memory encodedState = encodeState(state);

vm.expectRevert(hex"00000000000000000000000000000000000000000000000000000000f001ca11");
riscv.step(encodedState, proof, 0);
}
/* Helper methods */

function encodeState(State memory state) internal pure returns (bytes memory) {
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