Revert load instructions with reserved bits[14:12] = 111

[mininny]

The RISC-V specifications indicate the following in section "1.5.1 Expanded Instruction-Length Encoding".

The encoding with bits [14:12] set to "111" is reserved for future longer instruction encodings.

Moreover, it states the following about reserved instructions.

Reserved encodings are currently not defined but are saved for future standard extensions; once thus used, they become standard encodings.

The behavior upon decoding a reserved instruction is UNSPECIFIED.

Some platforms may require that opcodes reserved for standard use raise an illegalinstruction exception. Other platforms may permit reserved opcode space be used for nonconforming extensions

However, the RISCV implementations (solidity, slow, fast) support the reserved LOAD instruction that has bits [14:12] set to "111" and will have the same behaviour than "011". The same applies for "100", "101 and "110". This reserved instruction should not be supported.

Raise an illegal-instruction exception instead of executing this reserved instruction for which behavior is unspecified.

[codecov-commenter]

Codecov Report

Attention: Patch coverage is 40.00000% with 6 lines in your changes missing coverage. Please review.

Project coverage is 61.87%. Comparing base (cdddf9e) to head (66d0362).
Report is 2 commits behind head on master.

Files with missing lines	Patch %	Lines
rvgo/fast/vm.go	40.00%	2 Missing and 1 partial ⚠️
rvgo/slow/vm.go	40.00%	2 Missing and 1 partial ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##           master     #109      +/-   ##
==========================================
- Coverage   61.92%   61.87%   -0.06%     
==========================================
  Files          27       27              
  Lines        4116     4126      +10     
==========================================
+ Hits         2549     2553       +4     
- Misses       1428     1432       +4     
- Partials      139      141       +2     

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