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Make IF_SVE_FZ_2A and IF_SVE_HG_2A consistent with similar groups #100089

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Mar 22, 2024
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Make IF_SVE_FZ_2A and IF_SVE_HG_2A consistent with similar groups #100089

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14 changes: 7 additions & 7 deletions src/coreclr/jit/codegenarm64test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6329,16 +6329,16 @@ void CodeGen::genArm64EmitterUnitTestsSve()
INS_OPTS_SCALABLE_S); // URSQRTE <Zd>.S, <Pg>/M, <Zn>.S

// IF_SVE_FZ_2A
theEmitter->emitIns_R_R(INS_sve_sqcvtn, EA_SCALABLE, REG_V0, REG_V1); // SQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
theEmitter->emitIns_R_R(INS_sve_sqcvtun, EA_SCALABLE, REG_V6, REG_V7); // SQCVTUN <Zd>.H, {<Zn1>.S-<Zn2>.S }
theEmitter->emitIns_R_R(INS_sve_uqcvtn, EA_SCALABLE, REG_V14, REG_V15); // UQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
theEmitter->emitIns_R_R(INS_sve_sqcvtn, EA_SCALABLE, REG_V0, REG_V2); // SQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
theEmitter->emitIns_R_R(INS_sve_sqcvtun, EA_SCALABLE, REG_V6, REG_V8); // SQCVTUN <Zd>.H, {<Zn1>.S-<Zn2>.S }
theEmitter->emitIns_R_R(INS_sve_uqcvtn, EA_SCALABLE, REG_V14, REG_V16); // UQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
// IF_SVE_HG_2A
theEmitter->emitIns_R_R(INS_sve_bfcvtn, EA_SCALABLE, REG_V0, REG_V1); // BFCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
theEmitter->emitIns_R_R(INS_sve_fcvtn, EA_SCALABLE, REG_V2, REG_V3); // FCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
theEmitter->emitIns_R_R(INS_sve_fcvtnb, EA_SCALABLE, REG_V6, REG_V7); // FCVTNB <Zd>.B, {<Zn1>.S-<Zn2>.S }
theEmitter->emitIns_R_R(INS_sve_fcvtnt, EA_SCALABLE, REG_V14, REG_V15); // FCVTNT <Zd>.B, {<Zn1>.S-<Zn2>.S }
theEmitter->emitIns_R_R(INS_sve_bfcvtn, EA_SCALABLE, REG_V0, REG_V2); // BFCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
theEmitter->emitIns_R_R(INS_sve_fcvtn, EA_SCALABLE, REG_V2, REG_V4); // FCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
theEmitter->emitIns_R_R(INS_sve_fcvtnb, EA_SCALABLE, REG_V6, REG_V8); // FCVTNB <Zd>.B, {<Zn1>.S-<Zn2>.S }
theEmitter->emitIns_R_R(INS_sve_fcvtnt, EA_SCALABLE, REG_V14, REG_V16); // FCVTNT <Zd>.B, {<Zn1>.S-<Zn2>.S }
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED

// IF_SVE_GA_2A
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19 changes: 9 additions & 10 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1787,6 +1787,7 @@ void emitter::emitInsSanityCheck(instrDesc* id)
assert(id->idInsOpt() == INS_OPTS_SCALABLE_H);
assert(isVectorRegister(id->idReg1())); // nnnn
assert(isVectorRegister(id->idReg2())); // ddddd
assert(isEvenRegister(id->idReg2()));
assert(isScalableVectorSize(id->idOpSize()));
break;

Expand Down Expand Up @@ -1828,14 +1829,16 @@ void emitter::emitInsSanityCheck(instrDesc* id)

case IF_SVE_FZ_2A: // ................ ......nnnn.ddddd -- SME2 multi-vec extract narrow
assert(insOptsNone(id->idInsOpt()));
assert(isVectorRegister(id->idReg1())); // ddddd
assert(isLowVectorRegister(id->idReg2())); // nnnn
assert(isVectorRegister(id->idReg1())); // ddddd
assert(isVectorRegister(id->idReg2())); // nnnn
assert(isEvenRegister(id->idReg2()));
break;

case IF_SVE_HG_2A: // ................ ......nnnn.ddddd -- SVE2 FP8 downconverts
assert(insOptsNone(id->idInsOpt()));
assert(isVectorRegister(id->idReg1())); // ddddd
assert(isLowVectorRegister(id->idReg2())); // nnnn
assert(isVectorRegister(id->idReg1())); // ddddd
assert(isVectorRegister(id->idReg2())); // nnnn
assert(isEvenRegister(id->idReg2()));
break;

case IF_SVE_GD_2A: // .........x.xx... ......nnnnnddddd -- SVE2 saturating extract narrow
Expand Down Expand Up @@ -17276,19 +17279,15 @@ void emitter::emitDispInsHelp(
case IF_SVE_FZ_2A: // ................ ......nnnn.ddddd -- SME2 multi-vec extract narrow
{
emitDispSveReg(id->idReg1(), INS_OPTS_SCALABLE_H, true);
const unsigned baseRegNum = id->idReg2() - REG_FP_FIRST;
const regNumber regNum = (regNumber)((baseRegNum * 2) + REG_FP_FIRST);
emitDispSveConsecutiveRegList(regNum, 2, INS_OPTS_SCALABLE_S, false);
emitDispSveConsecutiveRegList(id->idReg2(), 2, INS_OPTS_SCALABLE_S, false);
break;
}

// <Zd>.B, {<Zn1>.H-<Zn2>.H }
case IF_SVE_HG_2A: // ................ ......nnnn.ddddd -- SVE2 FP8 downconverts
{
emitDispSveReg(id->idReg1(), INS_OPTS_SCALABLE_B, true);
const unsigned baseRegNum = id->idReg2() - REG_FP_FIRST;
const regNumber regNum = (regNumber)((baseRegNum * 2) + REG_FP_FIRST);
emitDispSveConsecutiveRegList(regNum, 2, INS_OPTS_SCALABLE_H, false);
emitDispSveConsecutiveRegList(id->idReg2(), 2, INS_OPTS_SCALABLE_H, false);
break;
}

Expand Down
17 changes: 17 additions & 0 deletions src/coreclr/jit/emitarm64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1187,6 +1187,23 @@ inline static bool isHighPredicateRegister(regNumber reg)
return (reg >= REG_PREDICATE_HIGH_FIRST) && (reg <= REG_PREDICATE_HIGH_LAST);
}

inline static bool isEvenRegister(regNumber reg)
{
if (isGeneralRegister(reg))
{
return ((reg - REG_INT_FIRST) % 2 == 0);
}
else if (isVectorRegister(reg))
{
return ((reg - REG_FP_FIRST) % 2) == 0;
}
else
{
assert(isPredicateRegister(reg));
return ((reg - REG_PREDICATE_FIRST) % 2) == 0;
}
}

inline static bool insOptsNone(insOpts opt)
{
return (opt == INS_OPTS_NONE);
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15 changes: 9 additions & 6 deletions src/coreclr/jit/emitarm64sve.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2118,8 +2118,9 @@ void emitter::emitInsSve_R_R(instruction ins,
case INS_sve_uqcvtn:
case INS_sve_sqcvtun:
assert(insOptsNone(opt));
assert(isVectorRegister(reg1)); // ddddd
assert(isLowVectorRegister(reg2)); // nnnn
assert(isVectorRegister(reg1)); // ddddd
assert(isVectorRegister(reg2)); // nnnn
assert(isEvenRegister(reg2));
fmt = IF_SVE_FZ_2A;
break;

Expand All @@ -2129,8 +2130,9 @@ void emitter::emitInsSve_R_R(instruction ins,
case INS_sve_fcvtnb:
unreached(); // TODO-SVE: Not yet supported.
assert(insOptsNone(opt));
assert(isVectorRegister(reg1)); // ddddd
assert(isLowVectorRegister(reg2)); // nnnn
assert(isVectorRegister(reg1)); // ddddd
assert(isVectorRegister(reg2)); // nnnn
assert(isEvenRegister(reg2));
fmt = IF_SVE_HG_2A;
break;

Expand Down Expand Up @@ -2542,6 +2544,7 @@ void emitter::emitInsSve_R_R_I(instruction ins,
isRightShift = emitInsIsVectorRightShift(ins);
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
assert(isEvenRegister(reg2));
assert(opt == INS_OPTS_SCALABLE_H);
assert(isRightShift); // These are always right-shift.
assert(isValidVectorShiftAmount(imm, EA_4BYTE, isRightShift));
Expand Down Expand Up @@ -10735,8 +10738,8 @@ BYTE* emitter::emitOutput_InstrSve(BYTE* dst, instrDesc* id)
case IF_SVE_FZ_2A: // ................ ......nnnn.ddddd -- SME2 multi-vec extract narrow
case IF_SVE_HG_2A: // ................ ......nnnn.ddddd -- SVE2 FP8 downconverts
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
code |= insEncodeReg_V_9_to_6(id->idReg2()); // nnnn
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
code |= insEncodeReg_V_9_to_6_Times_Two(id->idReg2()); // nnnn
dst += emitOutput_Instr(dst, code);
break;

Expand Down
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