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AXI sub tb integration -- compiles and passes smoke_test_hw_config
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@calebofearth
calebofearth committed Jul 25, 2024
1 parent e50cda0 commit 1ca975a
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Showing 36 changed files with 1,432 additions and 932 deletions.
2 changes: 1 addition & 1 deletion src/aes/config/aes.vf
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Expand Up @@ -88,4 +88,4 @@ ${CALIPTRA_ROOT}/src/aes/rtl/aes_shift_rows.sv
${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_single_column.sv
${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control.sv
${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_masking.sv
${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
4 changes: 4 additions & 0 deletions src/axi/config/axi_pkg.vf
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@@ -0,0 +1,4 @@
+incdir+${CALIPTRA_ROOT}/src/axi/rtl
${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv
${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv
${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv
24 changes: 24 additions & 0 deletions src/axi/config/axi_sub.vf
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@@ -0,0 +1,24 @@
+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/axi/rtl
${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv
${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv
${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v
${CALIPTRA_ROOT}/src/axi/rtl/skidbuffer.v
${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv
${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv
${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv
${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv
25 changes: 17 additions & 8 deletions src/axi/config/compile.yml
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@@ -1,22 +1,31 @@
---
provides: [axi_sub]
provides: [axi_pkg]
schema_version: 2.4.0
requires:
- libs
targets:
tb:
directories: [$COMPILE_ROOT/rtl]
files:
- $COMPILE_ROOT/rtl/axi_if.sv
- $COMPILE_ROOT/rtl/axi_pkg.sv
- $COMPILE_ROOT/rtl/axi_addr.v
- $COMPILE_ROOT/rtl/skidbuffer.v
- $COMPILE_ROOT/rtl/axi_sub_rd.sv
- $COMPILE_ROOT/rtl/axi_if.sv
rtl:
directories: [$COMPILE_ROOT/rtl]
files:
- $COMPILE_ROOT/rtl/axi_if.sv
- $COMPILE_ROOT/rtl/axi_pkg.sv
- $COMPILE_ROOT/rtl/axi_if.sv
---
provides: [axi_sub]
schema_version: 2.4.0
requires:
- libs
- axi_pkg
targets:
rtl:
directories: [$COMPILE_ROOT/rtl]
files:
- $COMPILE_ROOT/rtl/axi_addr.v
- $COMPILE_ROOT/rtl/skidbuffer.v
- $COMPILE_ROOT/rtl/axi_sub_rd.sv
- $COMPILE_ROOT/rtl/axi_sub_wr.sv
- $COMPILE_ROOT/rtl/axi_sub_arb.sv
- $COMPILE_ROOT/rtl/axi_sub.sv
tops: [axi_sub]
190 changes: 156 additions & 34 deletions src/axi/rtl/axi_if.sv
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Expand Up @@ -16,52 +16,52 @@
// Signals for a standard AXI4 compliant interface
//

interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, parameter integer IW = 3, parameter integer UW = 32);
interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, parameter integer IW = 3, parameter integer UW = 32) (input logic clk, input logic rst_n);

import axi_pkg::*;

// AXI AR
logic [AW-1:0] araddr;
logic [1:0] arburst;
logic [2:0] arsize;
logic [7:0] arlen;
logic [UW-1:0] aruser;
logic [IW-1:0] arid;
logic arlock;
logic arvalid;
logic arready;
logic [AW-1:0] araddr;
logic [$bits(axi_burst_e)-1:0] arburst;
logic [2:0] arsize;
logic [7:0] arlen;
logic [UW-1:0] aruser;
logic [IW-1:0] arid;
logic arlock;
logic arvalid;
logic arready;

// AXI R
logic [DW-1:0] rdata;
logic [1:0] rresp;
logic [IW-1:0] rid;
logic rlast;
logic rvalid;
logic rready;
logic [DW-1:0] rdata;
logic [$bits(axi_resp_e)-1:0] rresp;
logic [IW-1:0] rid;
logic rlast;
logic rvalid;
logic rready;

// AXI AW
logic [AW-1:0] awaddr;
logic [1:0] awburst;
logic [2:0] awsize;
logic [7:0] awlen;
logic [UW-1:0] awuser;
logic [IW-1:0] awid;
logic awlock;
logic awvalid;
logic awready;
logic [AW-1:0] awaddr;
logic [$bits(axi_burst_e)-1:0] awburst;
logic [2:0] awsize;
logic [7:0] awlen;
logic [UW-1:0] awuser;
logic [IW-1:0] awid;
logic awlock;
logic awvalid;
logic awready;

// AXI W
logic [DW-1:0] wdata;
logic [DW/8-1:0] wstrb;
logic wvalid;
logic wready;
logic wlast;
logic [DW-1:0] wdata;
logic [DW/8-1:0] wstrb;
logic wvalid;
logic wready;
logic wlast;

// AXI B
logic [1:0] bresp;
logic [IW-1:0] bid;
logic bvalid;
logic bready;
logic [$bits(axi_resp_e)-1:0] bresp;
logic [IW-1:0] bid;
logic bvalid;
logic bready;

// Modport for read manager
modport r_mgr (
Expand Down Expand Up @@ -155,4 +155,126 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
input bready
);

// Tasks
task rst_mgr();
araddr = '0;
arburst = AXI_BURST_FIXED;
arsize = '0;
arlen = '0;
aruser = '0;
arid = '0;
arlock = '0;
arvalid = '0;

rready = '0;

awaddr = '0;
awburst = AXI_BURST_FIXED;
awsize = '0;
awlen = '0;
awuser = '0;
awid = '0;
awlock = '0;
awvalid = '0;

wdata = '0;
wstrb = '0;
wvalid = '0;
wlast = '0;

bready = '0;
endtask

// TODO: handle IDs?
task get_read_beat(ref logic [DW-1:0] data,
ref axi_resp_e resp);
rready = 1;
do
@(posedge clk);
while (!rvalid);
data = rdata;
resp = axi_resp_e'(rresp);
rready = 0;
endtask

// Read: default to single beat of native data width
task axi_read(input logic [AW-1:0] addr,
input axi_burst_e burst = AXI_BURST_INCR,
input logic [2:0] size = $clog2(DW/8),
input logic [7:0] len = 0,
input logic [UW-1:0] user = UW'(0),
input logic [IW-1:0] id = IW'(0),
input logic lock = 1'b0,
ref logic [DW-1:0] data [],
ref axi_resp_e resp []);
axi_resp_e beat_resp;
logic [DW-1:0] beat_data;
while(!rst_n) @(posedge clk);
do begin
araddr = addr;
arburst = burst;
arsize = size;
arlen = len;
aruser = user;
arid = id;
arlock = lock;
arvalid = 1;
@(posedge clk);
end while(!arready);
for (int beat=0; beat <= len; beat++) begin
get_read_beat(beat_data, beat_resp);
data[beat] = beat_data;
resp[beat] = beat_resp;
end
endtask

task send_write_beat(input logic last,
input logic [DW-1:0] data,
input logic [DW/8-1:0] strb);
wvalid = 1;
wlast = last;
wdata = data;
wstrb = strb;
do
@(posedge clk);
while (!wready);
endtask

// TODO handle ID
task get_write_resp(output axi_resp_e resp);
bready = 1;
while(!bvalid) @(posedge clk);
resp = axi_resp_e'(bresp);
endtask

task axi_write( input logic [AW-1:0] addr,
input axi_burst_e burst = AXI_BURST_INCR,
input logic [2:0] size = $clog2(DW/8),
input logic [7:0] len = 0,
input logic [UW-1:0] user = UW'(0),
input logic [IW-1:0] id = IW'(0),
input logic lock = 1'b0,
const ref logic [DW-1:0] data [],
input logic use_strb = 0,
const ref logic [DW/8-1:0] strb [],
output axi_resp_e resp);
while(!rst_n) @(posedge clk);
do begin
awaddr = addr;
awburst = burst;
awsize = size;
awlen = len;
awuser = user;
awid = id;
awlock = lock;
awvalid = 1;
@(posedge clk);
end while(!awready);
fork
for (int beat=0; beat <= len; beat++)
send_write_beat(beat == len, data[beat], use_strb ? strb[beat] : {DW/8{1'b1}});
get_write_resp(resp);
join
endtask

endinterface
23 changes: 0 additions & 23 deletions src/axi/rtl/axi_pkg.sv
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Expand Up @@ -31,27 +31,4 @@ package axi_pkg;
AXI_RESP_DECERR = 2'b11
} axi_resp_e;

// Transaction context
typedef struct packed {
logic [AW-1:0] addr;
logic [1:0] burst;
logic [2:0] size;
logic [7:0] len;
logic [UW-1:0] user;
logic [IW-1:0] id;
logic lock;
} axi_ctx_t;

typedef struct packed {
logic [IW-1:0] id;
logic [UW-1:0] user;
axi_resp_e resp;
logic last;
} xfer_ctx_t;

typedef struct packed {
logic [AW-1:0] addr;
logic [AW-1:0] addr_mask;
} axi_ex_ctx_t;

endpackage
5 changes: 4 additions & 1 deletion src/axi/rtl/axi_sub.sv
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Expand Up @@ -67,7 +67,10 @@ module axi_sub import axi_pkg::*; #(
// Exclusive Access Signals
logic [ID_NUM-1:0] ex_clr;
logic [ID_NUM-1:0] ex_active;
axi_ex_ctx_t [ID_NUM-1:0] ex_ctx;
struct packed {
logic [AW-1:0] addr;
logic [AW-1:0] addr_mask;
} [ID_NUM-1:0] ex_ctx;

//Read Subordinate INF
logic r_dv;
Expand Down
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