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Device tree #47
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Regarding point number 1, to generate a memory-mapper configuration, the configuration needs to be loaded into a (TemplateHaskell) program. There are no Haskell packages to read device tree files from what I can tell, which opens up the question on how this case should be handled:
I think 1. would be a lot of work and we really only are interested in a few key numbers, so 2. seems like the better choice. With 2. we add another configuration layer on top and move the "source of truth" to a different file. To me it seems like 2. is less work and allows us to get started quicker, also we wouldn't have to maintain a package to read FDTs which are way overkill for this use case. |
I agree with that assessment. (2) seems like the way to go. We should pick either TOML or YAML; JSON always ends up being a pain due to it not supporting comments and multi-line strings. |
#67 mentions it partially implements this issue. What's still missing @cuddlefishie? |
Creating and reading the device tree works already, I think I wrote that it's a partial implementation to this issue because of the point 2. in my comment above! There is no central configuration file anywhere at the moment that configures both the hardware and the device tree, they have to be kept in sync manually at the moment |
#315 offers direct access to property values of a device tree specification in Haskell via TH. This should be sufficient to resolve this issue. |
Superseded by #481. |
ca418fcb Merge pull request #47 from clash-lang/lucas/move-stoptime-ndmreset 27c82690 Move `ndmreset` and `stoptime` from `JtagOut` to `CpuOut` 68886c88 Merge pull request #46 from clash-lang/run-clang-format a32dbc98 Add `clang-format-check` to ci 68ca4d0e Format with `clang-format` 9a676aa6 Add `clang` to nix shell 0d4be0e0 Merge pull request #45 from clash-lang/lucas/bump-jtag-interface 61c7719d Bump GHC versions on Docker images and rebuild 5f9a53c9 Add `.scala-build` to `.gitignore` 2c1ec3a3 Remove `openocd-vexriscv` from `nix` and `docker` deabc085 Switch to `openocd-vexriscv` and use `remote-bitbang` d987e396 Replace `DebugPlugin` with `EmbeddedRiscvJtag` 59298429 Add `nix` derivation for `openocv-riscv` 2dfda13f Add `.metals` to `.gitignore` 554f4af1 Bump scala and spinal version 720e5d44 Add execute permissions to `update-vexriscv.pu` ad6edb75 Merge pull request #44 from clash-lang/lucas/add-docker-readme 636ac968 Extend readme with CI info ac10433d Bump GHA actions (#43) 59215117 Merge pull request #42 from clash-lang/add-all-check e697bfdd Fix typo: ouput -> output e7e8e29c Add all check to CI git-subtree-dir: clash-vexriscv git-subtree-split: ca418fcb0024e12b4b2f9340d34aad47eaca370d
3a26b8bd Correcetly simulate passed time before first clock edge in verilator (#50) 51239127 Add post fetch step that removes `.git` (#48) ca418fcb Merge pull request #47 from clash-lang/lucas/move-stoptime-ndmreset 27c82690 Move `ndmreset` and `stoptime` from `JtagOut` to `CpuOut` 68886c88 Merge pull request #46 from clash-lang/run-clang-format a32dbc98 Add `clang-format-check` to ci 68ca4d0e Format with `clang-format` 9a676aa6 Add `clang` to nix shell 0d4be0e0 Merge pull request #45 from clash-lang/lucas/bump-jtag-interface 61c7719d Bump GHC versions on Docker images and rebuild 5f9a53c9 Add `.scala-build` to `.gitignore` 2c1ec3a3 Remove `openocd-vexriscv` from `nix` and `docker` deabc085 Switch to `openocd-vexriscv` and use `remote-bitbang` d987e396 Replace `DebugPlugin` with `EmbeddedRiscvJtag` 59298429 Add `nix` derivation for `openocv-riscv` 2dfda13f Add `.metals` to `.gitignore` 554f4af1 Bump scala and spinal version 720e5d44 Add execute permissions to `update-vexriscv.pu` ad6edb75 Merge pull request #44 from clash-lang/lucas/add-docker-readme 636ac968 Extend readme with CI info ac10433d Bump GHA actions (#43) 59215117 Merge pull request #42 from clash-lang/add-all-check e697bfdd Fix typo: ouput -> output e7e8e29c Add all check to CI git-subtree-dir: clash-vexriscv git-subtree-split: 3a26b8bdd1a1863030b89943d4bf229c2ce97831
3a26b8bd Correcetly simulate passed time before first clock edge in verilator (#50) 51239127 Add post fetch step that removes `.git` (#48) ca418fcb Merge pull request #47 from clash-lang/lucas/move-stoptime-ndmreset 27c82690 Move `ndmreset` and `stoptime` from `JtagOut` to `CpuOut` 68886c88 Merge pull request #46 from clash-lang/run-clang-format a32dbc98 Add `clang-format-check` to ci 68ca4d0e Format with `clang-format` 9a676aa6 Add `clang` to nix shell 0d4be0e0 Merge pull request #45 from clash-lang/lucas/bump-jtag-interface 61c7719d Bump GHC versions on Docker images and rebuild 5f9a53c9 Add `.scala-build` to `.gitignore` 2c1ec3a3 Remove `openocd-vexriscv` from `nix` and `docker` deabc085 Switch to `openocd-vexriscv` and use `remote-bitbang` d987e396 Replace `DebugPlugin` with `EmbeddedRiscvJtag` 59298429 Add `nix` derivation for `openocv-riscv` 2dfda13f Add `.metals` to `.gitignore` 554f4af1 Bump scala and spinal version 720e5d44 Add execute permissions to `update-vexriscv.pu` ad6edb75 Merge pull request #44 from clash-lang/lucas/add-docker-readme 636ac968 Extend readme with CI info ac10433d Bump GHA actions (#43) 59215117 Merge pull request #42 from clash-lang/add-all-check e697bfdd Fix typo: ouput -> output e7e8e29c Add all check to CI git-subtree-dir: clash-vexriscv git-subtree-split: 3a26b8bdd1a1863030b89943d4bf229c2ce97831
3a26b8bd Correcetly simulate passed time before first clock edge in verilator (#50) 51239127 Add post fetch step that removes `.git` (#48) ca418fcb Merge pull request #47 from clash-lang/lucas/move-stoptime-ndmreset 27c82690 Move `ndmreset` and `stoptime` from `JtagOut` to `CpuOut` 68886c88 Merge pull request #46 from clash-lang/run-clang-format a32dbc98 Add `clang-format-check` to ci 68ca4d0e Format with `clang-format` 9a676aa6 Add `clang` to nix shell 0d4be0e0 Merge pull request #45 from clash-lang/lucas/bump-jtag-interface 61c7719d Bump GHC versions on Docker images and rebuild 5f9a53c9 Add `.scala-build` to `.gitignore` 2c1ec3a3 Remove `openocd-vexriscv` from `nix` and `docker` deabc085 Switch to `openocd-vexriscv` and use `remote-bitbang` d987e396 Replace `DebugPlugin` with `EmbeddedRiscvJtag` 59298429 Add `nix` derivation for `openocv-riscv` 2dfda13f Add `.metals` to `.gitignore` 554f4af1 Bump scala and spinal version 720e5d44 Add execute permissions to `update-vexriscv.pu` ad6edb75 Merge pull request #44 from clash-lang/lucas/add-docker-readme 636ac968 Extend readme with CI info ac10433d Bump GHA actions (#43) 59215117 Merge pull request #42 from clash-lang/add-all-check e697bfdd Fix typo: ouput -> output e7e8e29c Add all check to CI git-subtree-dir: clash-vexriscv git-subtree-split: 3a26b8bdd1a1863030b89943d4bf229c2ce97831
3a26b8bd Correcetly simulate passed time before first clock edge in verilator (#50) 51239127 Add post fetch step that removes `.git` (#48) ca418fcb Merge pull request #47 from clash-lang/lucas/move-stoptime-ndmreset 27c82690 Move `ndmreset` and `stoptime` from `JtagOut` to `CpuOut` 68886c88 Merge pull request #46 from clash-lang/run-clang-format a32dbc98 Add `clang-format-check` to ci 68ca4d0e Format with `clang-format` 9a676aa6 Add `clang` to nix shell 0d4be0e0 Merge pull request #45 from clash-lang/lucas/bump-jtag-interface 61c7719d Bump GHC versions on Docker images and rebuild 5f9a53c9 Add `.scala-build` to `.gitignore` 2c1ec3a3 Remove `openocd-vexriscv` from `nix` and `docker` deabc085 Switch to `openocd-vexriscv` and use `remote-bitbang` d987e396 Replace `DebugPlugin` with `EmbeddedRiscvJtag` 59298429 Add `nix` derivation for `openocv-riscv` 2dfda13f Add `.metals` to `.gitignore` 554f4af1 Bump scala and spinal version 720e5d44 Add execute permissions to `update-vexriscv.pu` ad6edb75 Merge pull request #44 from clash-lang/lucas/add-docker-readme 636ac968 Extend readme with CI info ac10433d Bump GHA actions (#43) 59215117 Merge pull request #42 from clash-lang/add-all-check e697bfdd Fix typo: ouput -> output e7e8e29c Add all check to CI git-subtree-dir: clash-vexriscv git-subtree-split: 3a26b8bdd1a1863030b89943d4bf229c2ce97831
3a26b8bd Correcetly simulate passed time before first clock edge in verilator (#50) 51239127 Add post fetch step that removes `.git` (#48) ca418fcb Merge pull request #47 from clash-lang/lucas/move-stoptime-ndmreset 27c82690 Move `ndmreset` and `stoptime` from `JtagOut` to `CpuOut` 68886c88 Merge pull request #46 from clash-lang/run-clang-format a32dbc98 Add `clang-format-check` to ci 68ca4d0e Format with `clang-format` 9a676aa6 Add `clang` to nix shell 0d4be0e0 Merge pull request #45 from clash-lang/lucas/bump-jtag-interface 61c7719d Bump GHC versions on Docker images and rebuild 5f9a53c9 Add `.scala-build` to `.gitignore` 2c1ec3a3 Remove `openocd-vexriscv` from `nix` and `docker` deabc085 Switch to `openocd-vexriscv` and use `remote-bitbang` d987e396 Replace `DebugPlugin` with `EmbeddedRiscvJtag` 59298429 Add `nix` derivation for `openocv-riscv` 2dfda13f Add `.metals` to `.gitignore` 554f4af1 Bump scala and spinal version 720e5d44 Add execute permissions to `update-vexriscv.pu` ad6edb75 Merge pull request #44 from clash-lang/lucas/add-docker-readme 636ac968 Extend readme with CI info ac10433d Bump GHA actions (#43) 59215117 Merge pull request #42 from clash-lang/add-all-check e697bfdd Fix typo: ouput -> output e7e8e29c Add all check to CI git-subtree-dir: clash-vexriscv git-subtree-split: 3a26b8bdd1a1863030b89943d4bf229c2ce97831
3a26b8bd Correcetly simulate passed time before first clock edge in verilator (#50) 51239127 Add post fetch step that removes `.git` (#48) ca418fcb Merge pull request #47 from clash-lang/lucas/move-stoptime-ndmreset 27c82690 Move `ndmreset` and `stoptime` from `JtagOut` to `CpuOut` 68886c88 Merge pull request #46 from clash-lang/run-clang-format a32dbc98 Add `clang-format-check` to ci 68ca4d0e Format with `clang-format` 9a676aa6 Add `clang` to nix shell 0d4be0e0 Merge pull request #45 from clash-lang/lucas/bump-jtag-interface 61c7719d Bump GHC versions on Docker images and rebuild 5f9a53c9 Add `.scala-build` to `.gitignore` 2c1ec3a3 Remove `openocd-vexriscv` from `nix` and `docker` deabc085 Switch to `openocd-vexriscv` and use `remote-bitbang` d987e396 Replace `DebugPlugin` with `EmbeddedRiscvJtag` 59298429 Add `nix` derivation for `openocv-riscv` 2dfda13f Add `.metals` to `.gitignore` 554f4af1 Bump scala and spinal version 720e5d44 Add execute permissions to `update-vexriscv.pu` ad6edb75 Merge pull request #44 from clash-lang/lucas/add-docker-readme 636ac968 Extend readme with CI info ac10433d Bump GHA actions (#43) 59215117 Merge pull request #42 from clash-lang/add-all-check e697bfdd Fix typo: ouput -> output e7e8e29c Add all check to CI git-subtree-dir: clash-vexriscv git-subtree-split: 3a26b8bdd1a1863030b89943d4bf229c2ce97831
da3b01a2 Set cache path to Cabal store set in `shell.nix` (#65) 3f9758a1 Check whether Nix shell works on CI (#61) 9363f8d4 Merge pull request #63 from clash-lang/improve-expect-functions 79c5e34a Add timeout to expect functions ed39928d Add call stack to `waitForLine` f1d76ead Use `tail` instead of `streaming` to follow files (#64) e86580bf Remove enable from `cpu` (#58) c69899c2 Drop register on wishbone bus (#59) 1715fc73 Print `JTAG bridge ready` and wait for it to prevent race conditions (#57) 1ca5a69d Merge pull request #53 from clash-lang/add-fourmolu 5e11a6f6 Add `.git-blame-ignore-revs` 2bd141e6 Add fourmolu formatting 96ad7244 Use `HasCallStack` instead of manual source line tracking (#52) 3900cb07 Bump OpenOCD (#54) 3a26b8bd Correcetly simulate passed time before first clock edge in verilator (#50) 51239127 Add post fetch step that removes `.git` (#48) ca418fcb Merge pull request #47 from clash-lang/lucas/move-stoptime-ndmreset 27c82690 Move `ndmreset` and `stoptime` from `JtagOut` to `CpuOut` 68886c88 Merge pull request #46 from clash-lang/run-clang-format a32dbc98 Add `clang-format-check` to ci 68ca4d0e Format with `clang-format` 9a676aa6 Add `clang` to nix shell 0d4be0e0 Merge pull request #45 from clash-lang/lucas/bump-jtag-interface 61c7719d Bump GHC versions on Docker images and rebuild 5f9a53c9 Add `.scala-build` to `.gitignore` 2c1ec3a3 Remove `openocd-vexriscv` from `nix` and `docker` deabc085 Switch to `openocd-vexriscv` and use `remote-bitbang` d987e396 Replace `DebugPlugin` with `EmbeddedRiscvJtag` 59298429 Add `nix` derivation for `openocv-riscv` 2dfda13f Add `.metals` to `.gitignore` 554f4af1 Bump scala and spinal version 720e5d44 Add execute permissions to `update-vexriscv.pu` ad6edb75 Merge pull request #44 from clash-lang/lucas/add-docker-readme 636ac968 Extend readme with CI info ac10433d Bump GHA actions (#43) 59215117 Merge pull request #42 from clash-lang/add-all-check e697bfdd Fix typo: ouput -> output e7e8e29c Add all check to CI git-subtree-dir: clash-vexriscv git-subtree-split: da3b01a2fc91f55cec7fa33c1f07f88631d02ecf
As we can read on https://www.devicetree.org/
I think we shouldn't re-invent the wheel, and just repurpose
devicetree
to describe our memory-mapped registers.I envision a couple of aspects:
This way we don't have to create different firmwares for different configurations. Even before we have the memory-mapper live in hardware, we can already start on this issue to make the location of the character device configurable.
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