Circuit Refactoring

_unittest/test_21_Circuit.py

@@ -64,42 +64,42 @@ def teardown_class(self):
         gc.collect()
 
     def test_01_create_inductor(self):
-        myind = self.aedtapp.modeler.components.create_inductor(value=1e-9, location=[0.2, 0.2])
+        myind = self.aedtapp.modeler.schematic.create_inductor(value=1e-9, location=[0.2, 0.2])
         assert type(myind.id) is int
         assert myind.parameters["L"] == '1e-09'
 
     def test_02_create_resistor(self):
-        myres = self.aedtapp.modeler.components.create_resistor(value=50, location=[0.4, 0.2])
+        myres = self.aedtapp.modeler.schematic.create_resistor(value=50, location=[0.4, 0.2])
         assert type(myres.id) is int
         assert myres.parameters["R"] == '50'
 
     def test_03_create_capacitor(self):
-        mycap = self.aedtapp.modeler.components.create_capacitor(value=1e-12, location=[0.6, 0.2])
+        mycap = self.aedtapp.modeler.schematic.create_capacitor(value=1e-12, location=[0.6, 0.2])
         assert type(mycap.id) is int
         assert mycap.parameters["C"] == '1e-12'
 
     def test_04_getpin_names(self):
-        mycap2 = self.aedtapp.modeler.components.create_capacitor(value=1e-12)
-        pinnames = self.aedtapp.modeler.components.get_pins(mycap2)
-        pinnames2 = self.aedtapp.modeler.components.get_pins(mycap2.id)
-        pinnames3 = self.aedtapp.modeler.components.get_pins(mycap2.composed_name)
+        mycap2 = self.aedtapp.modeler.schematic.create_capacitor(value=1e-12)
+        pinnames = self.aedtapp.modeler.schematic.get_pins(mycap2)
+        pinnames2 = self.aedtapp.modeler.schematic.get_pins(mycap2.id)
+        pinnames3 = self.aedtapp.modeler.schematic.get_pins(mycap2.composed_name)
         assert pinnames2 == pinnames3
         assert type(pinnames) is list
         assert len(pinnames) == 2
 
     def test_05_getpin_location(self):
-        for el in self.aedtapp.modeler.components.components:
-            pinnames = self.aedtapp.modeler.components.get_pins(el)
+        for el in self.aedtapp.modeler.schematic.components:
+            pinnames = self.aedtapp.modeler.schematic.get_pins(el)
             for pinname in pinnames:
-                pinlocation = self.aedtapp.modeler.components.get_pin_location(el, pinname)
+                pinlocation = self.aedtapp.modeler.schematic.get_pin_location(el, pinname)
                 assert len(pinlocation) == 2
 
     def test_06_add_3dlayout_component(self):
-        myedb = self.aedtapp.modeler.components.add_subcircuit_3dlayout("Galileo_G87173_204")
+        myedb = self.aedtapp.modeler.schematic.add_subcircuit_3dlayout("Galileo_G87173_204")
         assert type(myedb.id) is int
 
     def test_07_add_hfss_component(self):
-        my_model, myname = self.aedtapp.modeler.components.create_field_model(
+        my_model, myname = self.aedtapp.modeler.schematic.create_field_model(
             "uUSB", "Setup1 : Sweep", ["usb_N_conn", "usb_N_pcb", "usb_P_conn", "usb_P_pcb"]
         )
         assert type(my_model) is int
@@ -142,10 +142,10 @@ def test_11_export_fullwave(self):
 
     def test_12_connect_components(self):
 
-        myind = self.aedtapp.modeler.components.create_inductor("L100", 1e-9)
-        myres = self.aedtapp.modeler.components.create_resistor("R100", 50)
-        mycap = self.aedtapp.modeler.components.create_capacitor("C100", 1e-12)
-        portname = self.aedtapp.modeler.components.create_interface_port("Port1")
+        myind = self.aedtapp.modeler.schematic.create_inductor("L100", 1e-9)
+        myres = self.aedtapp.modeler.schematic.create_resistor("R100", 50)
+        mycap = self.aedtapp.modeler.schematic.create_capacitor("C100", 1e-12)
+        portname = self.aedtapp.modeler.schematic.create_interface_port("Port1")
         assert "Port1" in portname.name
 
         assert self.aedtapp.modeler.connect_schematic_components(myind.id, myind.id, pinnum_second=2)
@@ -162,21 +162,21 @@ def test_12_connect_components(self):
         for pin in C1_pins:
             C1_pin2location[pin.name] = pin.location
 
-        portname = self.aedtapp.modeler.components.create_interface_port(
+        portname = self.aedtapp.modeler.schematic.create_interface_port(
             "P1_1", [L1_pin2location["n1"][0], L1_pin2location["n1"][1]]
         )
         assert "P1_1" in portname.name
-        portname = self.aedtapp.modeler.components.create_interface_port(
+        portname = self.aedtapp.modeler.schematic.create_interface_port(
             "P2_2", [C1_pin2location["negative"][0], C1_pin2location["negative"][1]]
         )
         assert "P2_2" in portname.name
 
         # create_page_port
-        portname = self.aedtapp.modeler.components.create_page_port(
+        portname = self.aedtapp.modeler.schematic.create_page_port(
             "Link_1", [L1_pin2location["n2"][0], L1_pin2location["n2"][1]]
         )
         assert "Link_1" in portname.name
-        portname = self.aedtapp.modeler.components.create_page_port(
+        portname = self.aedtapp.modeler.schematic.create_page_port(
             "Link_2", [C1_pin2location["positive"][0], C1_pin2location["positive"][1]], 180
         )
         assert "Link_2" in portname.name
@@ -297,3 +297,22 @@ def test_23_assign_power_sinusoidal_excitation_to_ports(self):
         settings = ["", "", "", "", "20W", "14GHz", "0s", "0", "0deg", "0Hz"]
         ports_list = ["P2_2"]
         assert self.aedtapp.assign_power_sinusoidal_excitation_to_ports(ports_list, settings)
+
+    def test_24_new_connect_components(self):
+        self.aedtapp.insert_design("Components")
+        myind = self.aedtapp.modeler.schematic.create_inductor("L100", 1e-9)
+        myres = self.aedtapp.modeler.components.create_resistor("R100", 50)
+        mycap = self.aedtapp.modeler.components.create_capacitor("C100", 1e-12)
+        myind2 = self.aedtapp.modeler.components.create_inductor("L101", 1e-9)
+        port = self.aedtapp.modeler.components.create_interface_port("Port1")
+        assert self.aedtapp.modeler.schematic.connect_components_in_series([myind, myres.composed_name])
+        assert self.aedtapp.modeler.schematic.connect_components_in_parallel([mycap, port, myind2.id])
+
+    def test_25_import_model(self):
+        self.aedtapp.insert_design("Touch_import")
+        touch = os.path.join(local_path, "example_models", "SSN_ssn.s6p")
+        t1 = self.aedtapp.modeler.schematic.create_touchsthone_component(touch)
+        assert t1
+        assert len(t1.pins) == 6
+        t2 = self.aedtapp.modeler.schematic.create_touchsthone_component(touch)
+        assert t2

_unittest/test_22_Circuit_DynamicLink.py

@@ -74,7 +74,7 @@ def test_01_save(self):
     @pytest.mark.skipif(config.get("skip_circuits", False), reason="Skipped because Desktop is crashing")
     def test_02_add_subcircuits_3dlayout(self):
         layout_design = "Galileo_G87173_205_cutout3"
-        hfss3Dlayout_comp = self.aedtapp.modeler.components.add_subcircuit_3dlayout(layout_design)
+        hfss3Dlayout_comp = self.aedtapp.modeler.schematic.add_subcircuit_3dlayout(layout_design)
         assert hfss3Dlayout_comp.id == 86
         assert hfss3Dlayout_comp
 
@@ -86,87 +86,87 @@ def test_03_add_subcircuits_hfss_link(self):
         assert len(pin_names) == 4
         assert "usb_P_pcb" in pin_names
 
-        hfss_comp = self.aedtapp.modeler.components.add_subcircuit_hfss_link(
+        hfss_comp = self.aedtapp.modeler.schematic.add_subcircuit_hfss_link(
             "uUSB", pin_names, source_project_path, src_design_name
         )
         assert hfss_comp.id == 87
         assert hfss_comp.composed_name == "CompInst@uUSB;87;3"
 
     @pytest.mark.skipif(config.get("skip_circuits", False), reason="Skipped because Desktop is crashing")
     def test_04_refresh_dynamic_link(self):
-        assert self.aedtapp.modeler.components.refresh_dynamic_link("uUSB")
+        assert self.aedtapp.modeler.schematic.refresh_dynamic_link("uUSB")
 
     @pytest.mark.skipif(config.get("skip_circuits", False), reason="Skipped because Desktop is crashing")
     def test_05_set_sim_option_on_hfss_subcircuit(self):
         hfss_comp = "CompInst@uUSB;87;3"
-        assert self.aedtapp.modeler.components.set_sim_option_on_hfss_subcircuit(hfss_comp)
-        assert self.aedtapp.modeler.components.set_sim_option_on_hfss_subcircuit(hfss_comp, option="interpolate")
-        assert not self.aedtapp.modeler.components.set_sim_option_on_hfss_subcircuit(hfss_comp, option="not_good")
+        assert self.aedtapp.modeler.schematic.set_sim_option_on_hfss_subcircuit(hfss_comp)
+        assert self.aedtapp.modeler.schematic.set_sim_option_on_hfss_subcircuit(hfss_comp, option="interpolate")
+        assert not self.aedtapp.modeler.schematic.set_sim_option_on_hfss_subcircuit(hfss_comp, option="not_good")
 
     @pytest.mark.skipif(config.get("skip_circuits", False), reason="Skipped because Desktop is crashing")
     def test_06_set_sim_solution_on_hfss_subcircuit(self):
         hfss_comp = "CompInst@uUSB;87;3"
-        assert self.aedtapp.modeler.components.set_sim_solution_on_hfss_subcircuit(hfss_comp)
+        assert self.aedtapp.modeler.schematic.set_sim_solution_on_hfss_subcircuit(hfss_comp)
 
     @pytest.mark.skipif(config.get("skip_circuits", False), reason="Skipped because Desktop is crashing")
     def test_07_create_page_port_and_interface_port(self):
         hfss_comp_id = 87
         hfss3Dlayout_comp_id = 86
-        hfssComp_pins = self.aedtapp.modeler.components.get_pins(hfss_comp_id)
+        hfssComp_pins = self.aedtapp.modeler.schematic.get_pins(hfss_comp_id)
         assert type(hfssComp_pins) is list
         assert len(hfssComp_pins) == 4
         hfss_pin2location = {}
         for pin in hfssComp_pins:
-            hfss_pin2location[pin] = self.aedtapp.modeler.components.get_pin_location(hfss_comp_id, pin)
+            hfss_pin2location[pin] = self.aedtapp.modeler.schematic.get_pin_location(hfss_comp_id, pin)
             assert len(hfss_pin2location[pin]) == 2
 
-        hfss3DlayoutComp_pins = self.aedtapp.modeler.components.get_pins(hfss3Dlayout_comp_id)
+        hfss3DlayoutComp_pins = self.aedtapp.modeler.schematic.get_pins(hfss3Dlayout_comp_id)
         assert type(hfssComp_pins) is list
         assert len(hfssComp_pins) == 4
         hfss3Dlayout_pin2location = {}
         for pin in hfss3DlayoutComp_pins:
-            hfss3Dlayout_pin2location[pin] = self.aedtapp.modeler.components.get_pin_location(hfss3Dlayout_comp_id, pin)
+            hfss3Dlayout_pin2location[pin] = self.aedtapp.modeler.schematic.get_pin_location(hfss3Dlayout_comp_id, pin)
             assert len(hfss3Dlayout_pin2location[pin]) == 2
 
         # Link 1 Creation
-        portname = self.aedtapp.modeler.components.create_page_port(
+        portname = self.aedtapp.modeler.schematic.create_page_port(
             "Link1", [hfss_pin2location["usb_N_conn"][0], hfss_pin2location["usb_N_conn"][1]], 180
         )
         assert "Link1" in portname.composed_name
-        portname = self.aedtapp.modeler.components.create_page_port(
+        portname = self.aedtapp.modeler.schematic.create_page_port(
             "Link1",
             [hfss3Dlayout_pin2location["J3B2.3.USBH2_DP_CH"][0], hfss3Dlayout_pin2location["J3B2.3.USBH2_DP_CH"][1]],
             180,
         )
         assert "Link1" in portname.composed_name
 
         # Link 2 Creation
-        portname = self.aedtapp.modeler.components.create_page_port(
+        portname = self.aedtapp.modeler.schematic.create_page_port(
             "Link2", [hfss_pin2location["usb_N_pcb"][0], hfss_pin2location["usb_N_pcb"][1]], 180
         )
         assert "Link2" in portname.composed_name
-        portname = self.aedtapp.modeler.components.create_page_port(
+        portname = self.aedtapp.modeler.schematic.create_page_port(
             "Link2",
             [hfss3Dlayout_pin2location["L3M1.3.USBH2_DN_CH"][0], hfss3Dlayout_pin2location["L3M1.3.USBH2_DN_CH"][1]],
             180,
         )
         assert "Link2" in portname.composed_name
 
         # Ports Creation
-        portname = self.aedtapp.modeler.components.create_interface_port(
+        portname = self.aedtapp.modeler.schematic.create_interface_port(
             "Excitation_1", [hfss_pin2location["USB_VCC_T1"][0], hfss_pin2location["USB_VCC_T1"][1]]
         )
         assert "Excitation_1" in portname.composed_name
-        portname = self.aedtapp.modeler.components.create_interface_port(
+        portname = self.aedtapp.modeler.schematic.create_interface_port(
             "Excitation_2", [hfss_pin2location["usb_P_pcb"][0], hfss_pin2location["usb_P_pcb"][1]]
         )
         assert "Excitation_2" in portname.composed_name
-        portname = self.aedtapp.modeler.components.create_interface_port(
+        portname = self.aedtapp.modeler.schematic.create_interface_port(
             "Port_1",
             [hfss3Dlayout_pin2location["L3M1.2.USBH2_DP_CH"][0], hfss3Dlayout_pin2location["L3M1.2.USBH2_DP_CH"][1]]
         )
         assert "Port_1" in portname.composed_name
-        portname = self.aedtapp.modeler.components.create_interface_port(
+        portname = self.aedtapp.modeler.schematic.create_interface_port(
             "Port_2",
             [hfss3Dlayout_pin2location["J3B2.2.USBH2_DN_CH"][0], hfss3Dlayout_pin2location["J3B2.2.USBH2_DN_CH"][1]]
         )

_unittest/test_26_emit.py

@@ -65,7 +65,7 @@ def test_connect_components(self):
 
     @pytest.mark.skipif(config["build_machine"], reason="Not functional in non-graphical mode")
     def test_radio_component(self):
-        radio = self.aedtapp.modeler.components.create_component("New Radio")
+        radio = self.aedtapp.modeler.schematic.create_component("New Radio")
         # default radio has 1 Tx channel and 1 Rx channel
         assert radio.has_rx_channels()
         assert radio.has_tx_channels()

_unittest/test_34_Simplorer.py

@@ -27,28 +27,28 @@ def teardown_class(self):
         gc.collect()
 
     def test_01_create_resistor(self):
-        id = self.aedtapp.modeler.components.create_resistor("Resistor1", 10, [0, 0])
+        id = self.aedtapp.modeler.schematic.create_resistor("Resistor1", 10, [0, 0])
         assert id.parameters["R"] == "10"
 
     def test_02_create_inductor(self):
-        id = self.aedtapp.modeler.components.create_inductor("Inductor1", 1.5, [0.25, 0])
+        id = self.aedtapp.modeler.schematic.create_inductor("Inductor1", 1.5, [0.25, 0])
         assert id.parameters["L"] == "1.5"
 
     def test_03_create_capacitor(self):
-        id = self.aedtapp.modeler.components.create_capacitor("Capacitor1", 7.5, [0.5, 0])
+        id = self.aedtapp.modeler.schematic.create_capacitor("Capacitor1", 7.5, [0.5, 0])
         assert id.parameters["C"] == "7.5"
 
     def test_04_create_diode(self):
-        id = self.aedtapp.modeler.components.create_diode("Diode1")
+        id = self.aedtapp.modeler.schematic.create_diode("Diode1")
         assert id.parameters["VF"] == "0.8V"
 
     def test_05_create_npn(self):
-        name = self.aedtapp.modeler.components.create_npn("NPN")
+        name = self.aedtapp.modeler.schematic.create_npn("NPN")
         # Get component info by part name
         assert name.parameters["VF"] == "0.8V"
 
     def test_06_create_pnp(self):
-        id = self.aedtapp.modeler.components.create_pnp("PNP")
+        id = self.aedtapp.modeler.schematic.create_pnp("PNP")
         assert id.parameters["VF"] == "0.8V"
 
     def test_07_import_netlist(self):

examples/06-Multiphysics/Hfss_Mechanical.py

@@ -46,7 +46,7 @@
 # Starts Circuit and add Hfss dynamic link component to it.
 
 circuit = Circuit()
-hfss_comp = circuit.modeler.components.add_subcircuit_hfss_link("MyHfss", pin_names, hfss.project_file,
+hfss_comp = circuit.modeler.schematic.add_subcircuit_hfss_link("MyHfss", pin_names, hfss.project_file,
                                                                               hfss.design_name)
 
 ###############################################################################
@@ -56,10 +56,10 @@
 # argument of set_sim_option_on_hfss_subcircuit can be the component name, the component id or
 # the component object.
 
-circuit.modeler.components.refresh_dynamic_link("MyHfss")
-circuit.modeler.components.set_sim_option_on_hfss_subcircuit(hfss_comp)
+circuit.modeler.schematic.refresh_dynamic_link("MyHfss")
+circuit.modeler.schematic.set_sim_option_on_hfss_subcircuit(hfss_comp)
 hfss_setup_name = hfss.setups[0].name + " : " + hfss.setups[0].sweeps[0].name
-circuit.modeler.components.set_sim_solution_on_hfss_subcircuit(hfss_comp.composed_name, hfss_setup_name)
+circuit.modeler.schematic.set_sim_solution_on_hfss_subcircuit(hfss_comp.composed_name, hfss_setup_name)
 
 ###############################################################################
 # Create Ports and Excitations
@@ -68,13 +68,13 @@
 # Voltage source on input port.
 
 
-circuit.modeler.components.create_interface_port("Excitation_1",
+circuit.modeler.schematic.create_interface_port("Excitation_1",
                                                  [hfss_comp.pins[0].location[0], hfss_comp.pins[0].location[1]])
-circuit.modeler.components.create_interface_port("Excitation_2",
+circuit.modeler.schematic.create_interface_port("Excitation_2",
                                                  [hfss_comp.pins[1].location[0], hfss_comp.pins[1].location[1]])
-circuit.modeler.components.create_interface_port("Port_1",
+circuit.modeler.schematic.create_interface_port("Port_1",
                                                  [hfss_comp.pins[2].location[0], hfss_comp.pins[2].location[1]])
-circuit.modeler.components.create_interface_port("Port_2",
+circuit.modeler.schematic.create_interface_port("Port_2",
                                                  [hfss_comp.pins[3].location[0], hfss_comp.pins[3].location[1]])
 
 voltage = 1