NimBLE AFR update and provision to use IRAM memory as 8-bit addressab…

…le memory region (aws#1713)

* NimBLE AFR: Update esp-idf submodule to include Host based Privacy (RPA)
* NimBLE AFR: Add support to IRAM allocation strategy

Added IRAM allocation provision under nimble_platform_mem_malloc()

* esp32/mbedtls: Added in/out buffer allocation strategy

"Internal IRAM" strategy allocates in/out buffers in IRAM thus
saving memory in DRAM.

To select this strategy:

idf.py menuconfig -> Component config -> ESP32 Specific -> Enable IRAM as 8 bit accessible memory

idf.py menuconfig -> Component config -> mbedTLS -> Memory allocation strategy -> Internal IRAM

Co-authored-by: Prasad Alatkar <prasad.alatkar@espressif.com>

vendors/espressif/boards/esp32/aws_demos/sdkconfig

@@ -175,6 +175,8 @@ CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD=20
 CONFIG_BLUEDROID_ENABLED=
 CONFIG_BT_RESERVE_DRAM=0xdb5c
 CONFIG_NIMBLE_ENABLED=y
+CONFIG_NIMBLE_MEM_ALLOC_MODE_INTERNAL=y
+CONFIG_NIMBLE_MEM_ALLOC_MODE_DEFAULT=
 CONFIG_NIMBLE_MAX_CONNECTIONS=1
 CONFIG_NIMBLE_MAX_BONDS=3
 CONFIG_NIMBLE_MAX_CCCDS=10
@@ -199,6 +201,12 @@ CONFIG_NIMBLE_ACL_BUF_SIZE=255
 CONFIG_NIMBLE_HCI_EVT_BUF_SIZE=70
 CONFIG_NIMBLE_HCI_EVT_HI_BUF_COUNT=30
 CONFIG_NIMBLE_HCI_EVT_LO_BUF_COUNT=8
+CONFIG_NIMBLE_MSYS1_BLOCK_COUNT=12
+CONFIG_NIMBLE_HS_FLOW_CTRL=y
+CONFIG_NIMBLE_HS_FLOW_CTRL_ITVL=1000
+CONFIG_NIMBLE_HS_FLOW_CTRL_THRESH=2
+CONFIG_NIMBLE_HS_FLOW_CTRL_TX_ON_DISCONNECT=y
+CONFIG_NIMBLE_RPA_TIMEOUT=900
 CONFIG_NIMBLE_MESH=
 CONFIG_NIMBLE_CRYPTO_STACK_MBEDTLS=y
 
@@ -309,6 +317,7 @@ CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
 CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
 CONFIG_ESP32_RTCDATA_IN_FAST_MEM=
 CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
+CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=
 
 #
 # Wi-Fi

vendors/espressif/boards/esp32/aws_tests/sdkconfig

@@ -175,6 +175,8 @@ CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD=20
 CONFIG_BLUEDROID_ENABLED=
 CONFIG_BT_RESERVE_DRAM=0xdb5c
 CONFIG_NIMBLE_ENABLED=y
+CONFIG_NIMBLE_MEM_ALLOC_MODE_INTERNAL=y
+CONFIG_NIMBLE_MEM_ALLOC_MODE_DEFAULT=
 CONFIG_NIMBLE_MAX_CONNECTIONS=1
 CONFIG_NIMBLE_MAX_BONDS=3
 CONFIG_NIMBLE_MAX_CCCDS=10
@@ -199,6 +201,12 @@ CONFIG_NIMBLE_ACL_BUF_SIZE=255
 CONFIG_NIMBLE_HCI_EVT_BUF_SIZE=70
 CONFIG_NIMBLE_HCI_EVT_HI_BUF_COUNT=30
 CONFIG_NIMBLE_HCI_EVT_LO_BUF_COUNT=8
+CONFIG_NIMBLE_MSYS1_BLOCK_COUNT=12
+CONFIG_NIMBLE_HS_FLOW_CTRL=y
+CONFIG_NIMBLE_HS_FLOW_CTRL_ITVL=1000
+CONFIG_NIMBLE_HS_FLOW_CTRL_THRESH=2
+CONFIG_NIMBLE_HS_FLOW_CTRL_TX_ON_DISCONNECT=y
+CONFIG_NIMBLE_RPA_TIMEOUT=900
 CONFIG_NIMBLE_MESH=
 CONFIG_NIMBLE_CRYPTO_STACK_MBEDTLS=y
 
@@ -309,6 +317,7 @@ CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
 CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
 CONFIG_ESP32_RTCDATA_IN_FAST_MEM=
 CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
+CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=
 
 #
 # Wi-Fi

vendors/espressif/boards/esp32/components/mbedtls/Kconfig

@@ -13,6 +13,7 @@ choice MBEDTLS_MEM_ALLOC_MODE
               behavior in ESP-IDF
             - Custom allocation mode, by overwriting calloc()/free() using
               mbedtls_platform_set_calloc_free() function
+            - Internal IRAM memory wherever applicable else internal DRAM
 
         Recommended mode here is always internal, since that is most preferred
         from security perspective. But if application requirement does not
@@ -32,6 +33,16 @@ config MBEDTLS_DEFAULT_MEM_ALLOC
 config MBEDTLS_CUSTOM_MEM_ALLOC
     bool "Custom alloc mode"
 
+config MBEDTLS_IRAM_8BIT_MEM_ALLOC
+    bool "Internal IRAM"
+    depends on ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+    help
+        Allows to use IRAM memory region as 8bit accessible region.
+
+        TLS input and output buffers will be allocated in IRAM section which is 32bit aligned
+        memory. Every unaligned (8bit or 16bit) access will result in an exception
+        and incur penalty of certain clock cycles per unaligned read/write.
+
 endchoice #MBEDTLS_MEM_ALLOC_MODE
 
 config MBEDTLS_SSL_MAX_CONTENT_LEN

vendors/espressif/boards/esp32/components/mbedtls/port/esp_mem.c

@@ -25,6 +25,16 @@ IRAM_ATTR void *esp_mbedtls_mem_calloc(size_t n, size_t size)
     return heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
 #elif CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC
     return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT);
+#elif CONFIG_MBEDTLS_IRAM_8BIT_MEM_ALLOC
+#ifdef CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN
+    if ((n*size) >= CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN || (n*size) >= CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN) {
+#else
+    if ((n*size) >= CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN) {
+#endif
+        return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
+    } else {
+        return heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
+    }
 #else
     return calloc(n, size);
 #endif