Non-synthesizable "#1" in generated rtl

[kdloe]

Is there a option to not have the "#1" in the generated rtl?

//------- reg assigns for axirdl_shm_intm
always_ff @ (posedge clk or negedge sig_ordtreg_rst_n) begin
if (! sig_ordtreg_rst_n) begin
rg_axirdl_shm_intm_err_int <= #1 1'd0;
end
else begin
rg_axirdl_shm_intm_err_int <= #1 reg_axirdl_shm_intm_err_int_next;
end
end

[sdnellen]

No option to remove these currently. What synth tool has issues with pound 1?

[kdloe]

Not that a synth tool has an issue with it, it shows up in our LINT checks as non-synthesizable and may contribute to sim vs silicon mismatches. We have a mix of legacy verilog code and newer system verilog code and do not allow #1 due to a past history of simulators that had issues with delta delays. Even though today's tools have less issues, our methodology is that the UVCs take care of any timing issues at the verif boundary. We also do not want surprise timescale differences.

[sdnellen]

Added include_sequential_assign_delays param in v190312 - set to false to remove these pound 1 delays (seems to gen correctly but not tested).

[sdnellen]

Try release 190524.01.

[neenuprince]

Tried the new Release and we don't see the #1's anymore

[kdloe]

Closing