added include_sequential_assign_delays sv output parameter

if true (default) a pound 1 delay is included in sequential assign
statements.  If false, no delay is added.  Addresses issue #54.

example.parms

@@ -64,6 +64,7 @@ output systemverilog {
     use_global_dv_bind_controls = true   // if true diagnostic dv bind module settings will be controlled by global packages 
     //include_addr_monitor = true       // generate io to monitor decoder transactions to a specified address range 
     generate_iwrap_xform_modules = false // generate common wrapper transform modules
+    //include_sequential_assign_delays = true // include #1 delay on sequential assigns
 }
 
 // jspec output parameters

src/ordt/extract/Ordt.java

@@ -34,7 +34,7 @@
 
 public class Ordt {
 
-	private static String version = "190211.01";
+	private static String version = "190312.01";
 	private static DebugController debug = new MyDebugController(); // override design annotations, input/output files
 
 	public enum InputType { RDL, JSPEC };

src/ordt/output/systemverilog/SystemVerilogLogicModule.java

@@ -142,11 +142,11 @@ else if (fieldProperties.hasRef(RhsRefType.RESET_SIGNAL)) {
 					   MsgUtils.errorMessage("reset signal " + resetSignalName + " for field " + fieldProperties.getInstancePath() + " has not been defined");
 			   }
 			   addReset(resetSignalName, resetSignalActiveLow);
-			   addResetAssign(regProperties.getBaseName(), resetSignalName, fieldRegisterName + " <= #1 " + getResetValueString() + ";");  // ff reset assigns			   
+			   addResetAssign(regProperties.getBaseName(), resetSignalName, fieldRegisterName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "" + getResetValueString() + ";");  // ff reset assigns			   
 		   }
 		   else if (!ExtParameters.sysVerSuppressNoResetWarnings()) MsgUtils.warnMessage("field " + fieldProperties.getInstancePath() + " has no reset defined");
 
-		   addRegAssign(regProperties.getBaseName(),  fieldRegisterName + " <= #1  " + fieldRegisterNextName + ";");  // assign next to flop
+		   addRegAssign(regProperties.getBaseName(),  fieldRegisterName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + fieldRegisterNextName + ";");  // assign next to flop
 	}
 
 	/** create statements to set value of next based on field settings */ 
@@ -426,7 +426,7 @@ else if (fieldProperties.hasRef(RhsRefType.INTR_MASK)) {
 			   // if not LEVEL, need to store previous intr value
 			   if (fieldProperties.getIntrType() != FieldProperties.IntrType.LEVEL) {
 				   addVectorReg(prevIntrName, 0, fieldProperties.getFieldWidth());
-				   addRegAssign(regProperties.getBaseName(), prevIntrName  +  " <= #1 " + hwToLogicIntrName + ";");
+				   addRegAssign(regProperties.getBaseName(), prevIntrName  +  " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "" + hwToLogicIntrName + ";");
 				   // if posedge detect
 				   if (fieldProperties.getIntrType() == FieldProperties.IntrType.POSEDGE) 
 					   detectStr = "(" + hwToLogicIntrName + " & ~" + prevIntrName + ")";
@@ -457,7 +457,7 @@ else if (fieldProperties.getIntrStickyType() == FieldProperties.IntrStickyType.S
 	       if (ExtParameters.sysVerPulseIntrOnClear()) {
 			   String intrDlyName = fieldProperties.getFullSignalName(DefSignalType.INTR_DLY); 	   
 			   addVectorReg(intrDlyName, 0, fieldProperties.getFieldWidth());
-			   addRegAssign(regProperties.getBaseName(), intrDlyName  +  " <= #1 " + fieldRegisterName + ";");
+			   addRegAssign(regProperties.getBaseName(), intrDlyName  +  " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "" + fieldRegisterName + ";");
 		       addPrecCombinAssign(regProperties.getBaseName(), hwPrecedence, intrClear + " = " + intrClear  + orStr + intrDlyName + " & ~" + fieldRegisterName + endStr);  // negedge detect
 	       }
 
@@ -511,7 +511,7 @@ private void genCounterWriteStmts(boolean hwPrecedence) {
 				   addHwScalar(DefSignalType.L2H_OVERFLOW);   // add hw overflow output
 				   addScalarReg(logicToHwOverflowName);  
 				   addRegAssign(regProperties.getBaseName(), logicToHwOverflowName +
-						   " <= #1 " + nextCountName + "[" + fieldWidth + "] & ~" +  logicToHwOverflowName + ";");  // only active for one cycle  
+						   " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "" + nextCountName + "[" + fieldWidth + "] & ~" +  logicToHwOverflowName + ";");  // only active for one cycle  
 			   }
 
 			   // if a ref is being used for increment assign it, else add an input
@@ -534,7 +534,7 @@ private void genCounterWriteStmts(boolean hwPrecedence) {
 				   addHwScalar(DefSignalType.L2H_UNDERFLOW);   // add hw underflow output
 				   addScalarReg(logicToHwUnderflowName);  
 				   addRegAssign(regProperties.getBaseName(), logicToHwUnderflowName +
-						   " <= #1 " + nextCountName + "[" + fieldWidth + "] & ~" +  logicToHwUnderflowName + ";");  // only active for one cycle  
+						   " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "" + nextCountName + "[" + fieldWidth + "] & ~" +  logicToHwUnderflowName + ";");  // only active for one cycle  
 			   }
 
 			   // if a ref is being used for decrement assign it, else add an input

src/ordt/output/systemverilog/SystemVerilogTestBuilder.java

@@ -378,7 +378,7 @@ private void addSimStartBlocks(int clkPeriod) {
 		   	benchtop.addStatement("always @(*)");
 		   	benchtop.addStatement("   gclk = CLK & delayed_gclk_enable;");
 		   	benchtop.addStatement("always @(posedge CLK)");
-		   	benchtop.addStatement("   delayed_gclk_enable <= #1 gclk_enable;");
+		   	benchtop.addStatement("   delayed_gclk_enable <= " + ExtParameters.sysVerSequentialAssignDelayString() + "gclk_enable;");
 		}
 		else {
 		   	// generate clocks

src/ordt/parameters/ExtParameters.java

@@ -150,6 +150,7 @@ public void set(String valStr) {
 		initBooleanParameter("use_global_dv_bind_controls", false); 
 		initBooleanParameter("include_addr_monitor", false); 
 		initBooleanParameter("generate_iwrap_xform_modules", true); 
+		initBooleanParameter("include_sequential_assign_delays", true); 
 
 		// ---- rdl output defaults
 		initBooleanParameter("root_component_is_instanced", true); 
@@ -813,7 +814,11 @@ public static boolean sysVerIncludeAddrMonitor() {
 	public static boolean sysVerGenerateIwrapXformModules() {
 		return getBooleanParameter("generate_iwrap_xform_modules");
 	}
-
+
+	public static String sysVerSequentialAssignDelayString() {
+		return getBooleanParameter("include_sequential_assign_delays")? "#1 " : "";
+	}
+
 	// bench parameter getters
 
 	public static Boolean sysVerGenerateExternalRegs() {

src/ordt/parse/grammars/CommonExtParms.g4

@@ -151,6 +151,7 @@ ext_parm_defs
    | 'use_global_dv_bind_controls' EQ bool 
    | 'include_addr_monitor' EQ bool 
    | 'generate_iwrap_xform_modules' EQ bool 
+   | 'include_sequential_assign_delays' EQ bool
    ;
 
  systemverilog_wrapper_info