Updated bitstreams to latest version of video core.

zwenergy · Sep 3, 2023 · 7b44c3f · 7b44c3f
1 parent a0d6920
commit 7b44c3f
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Showing 6 changed files with 5 additions and 5 deletions.
diff --git a/bitstream/default_1080p.bit b/bitstream/default_1080p.bit
diff --git a/bitstream/default_480p.bit b/bitstream/default_480p.bit
diff --git a/bitstream/default_720p.bit b/bitstream/default_720p.bit
diff --git a/hdl/definePackage.sv b/hdl/definePackage.sv
@@ -2,8 +2,8 @@
 //-- Title: Define Package
 //-- Author: zwenergy
 //-----------------------------------------------------------------------
-`define RES0_1080P
-`define SCALE6
+`define RES0_480P
+`define SCALE3
 
 package definePackage;
   localparam AUDIO_BIT_WIDTH = 16;

diff --git a/hdl/osd.vhd b/hdl/osd.vhd
@@ -68,8 +68,8 @@ type tMenuFrame is array( 0 to MENU_HEIGHTFIELDS - 1 ) of tLine;
 signal mainMenu : tMenuFrame := (
 -- One empty line
 ( 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 ),
--- GBAHD v1.3I
-( 00, 00, 00, 00, 00, 00, 00, 00, 07, 02, 01, 08, 04, 00, 22, 27, 36, 29, 09, 00, 00, 00, 00, 00, 00, 00, 00 ),
+-- GBAHD v1.3J
+( 00, 00, 00, 00, 00, 00, 00, 00, 07, 02, 01, 08, 04, 00, 22, 27, 36, 29, 10, 00, 00, 00, 00, 00, 00, 00, 00 ),
 -- One empty line
 ( 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 ),
 -- PXL GRID

diff --git a/hdl/pins.xdc b/hdl/pins.xdc
@@ -151,4 +151,4 @@ create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
 set_false_path -from [get_clocks pxlClkInt] -to [get_clocks clk]
 
 # Set USR_ACCESS register.
-set_property BITSTREAM.CONFIG.USR_ACCESS 0x312E3349 [current_design]
+set_property BITSTREAM.CONFIG.USR_ACCESS 0x312E334A [current_design]