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Arch arm v8m mpu remove hal #8467

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Jul 3, 2018
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Arch arm v8m mpu remove hal #8467

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0745568
arch: arm: Remove redundant HAL definition for ARM MPU
ioannisg Jun 19, 2018
3b6f67b
arch: arm: use CMSIS bitset flags for MPU attribute definitions
ioannisg Jun 19, 2018
b3753f0
arch: arm: beetle: duplicate ARM MPU registers' definition
ioannisg Jun 19, 2018
960de32
arch: arm: move ARMv7-m specific content in corresponding header file
ioannisg Jun 19, 2018
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40 changes: 19 additions & 21 deletions arch/arm/core/cortex_m/mpu/arm_mpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,6 @@
#include <logging/sys_log.h>
#include <linker/linker-defs.h>

#define ARM_MPU_DEV ((volatile struct arm_mpu *) ARM_MPU_BASE)

static inline u8_t _get_num_regions(void)
{
#if defined(CONFIG_CPU_CORTEX_M0PLUS) || \
Expand All @@ -26,7 +24,7 @@ static inline u8_t _get_num_regions(void)
*/
return 8;
#else
u32_t type = ARM_MPU_DEV->type;
u32_t type = MPU->TYPE;

type = (type & 0xFF00) >> 8;

Expand All @@ -43,11 +41,11 @@ static void _region_init(u32_t index, u32_t region_addr,
u32_t region_attr)
{
/* Select the region you want to access */
ARM_MPU_DEV->rnr = index;
MPU->RNR = index;
/* Configure the region */
ARM_MPU_DEV->rbar = (region_addr & MPU_RBAR_ADDR_Msk)
MPU->RBAR = (region_addr & MPU_RBAR_ADDR_Msk)
| MPU_RBAR_VALID_Msk | index;
ARM_MPU_DEV->rasr = region_attr | MPU_RASR_ENABLE_Msk;
MPU->RASR = region_attr | MPU_RASR_ENABLE_Msk;
SYS_LOG_DBG("[%d] 0x%08x 0x%08x", index, region_addr, region_attr);
}

Expand Down Expand Up @@ -157,9 +155,9 @@ static inline void _disable_region(u32_t r_index)
_get_num_regions());
SYS_LOG_DBG("disable region 0x%x", r_index);
/* Disable region */
ARM_MPU_DEV->rnr = r_index;
ARM_MPU_DEV->rbar = 0;
ARM_MPU_DEV->rasr = 0;
MPU->RNR = r_index;
MPU->RBAR = 0;
MPU->RASR = 0;
}

/**
Expand All @@ -170,9 +168,9 @@ static inline void _disable_region(u32_t r_index)
*/
static inline int _is_enabled_region(u32_t r_index)
{
ARM_MPU_DEV->rnr = r_index;
MPU->RNR = r_index;

return ARM_MPU_DEV->rasr & MPU_RASR_ENABLE_Msk;
return MPU->RASR & MPU_RASR_ENABLE_Msk;
}

/**
Expand All @@ -187,9 +185,9 @@ static inline int _is_in_region(u32_t r_index, u32_t start, u32_t size)
u32_t r_size_lshift;
u32_t r_addr_end;

ARM_MPU_DEV->rnr = r_index;
r_addr_start = ARM_MPU_DEV->rbar & MPU_RBAR_ADDR_Msk;
r_size_lshift = ((ARM_MPU_DEV->rasr & MPU_RASR_SIZE_Msk) >>
MPU->RNR = r_index;
r_addr_start = MPU->RBAR & MPU_RBAR_ADDR_Msk;
r_size_lshift = ((MPU->RASR & MPU_RASR_SIZE_Msk) >>
MPU_RASR_SIZE_Pos) + 1;
r_addr_end = r_addr_start + (1 << r_size_lshift) - 1;

Expand All @@ -210,7 +208,7 @@ void arm_core_mpu_enable(void)
/* Enable MPU and use the default memory map as a
* background region for privileged software access.
*/
ARM_MPU_DEV->ctrl = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
}

/**
Expand All @@ -219,7 +217,7 @@ void arm_core_mpu_enable(void)
void arm_core_mpu_disable(void)
{
/* Disable MPU */
ARM_MPU_DEV->ctrl = 0;
MPU->CTRL = 0;
}

/**
Expand Down Expand Up @@ -358,8 +356,8 @@ static inline int _is_user_accessible_region(u32_t r_index, int write)
{
u32_t r_ap;

ARM_MPU_DEV->rnr = r_index;
r_ap = ARM_MPU_DEV->rasr & MPU_RASR_AP_Msk;
MPU->RNR = r_index;
r_ap = MPU->RASR & MPU_RASR_AP_Msk;

/* always return true if this is the thread stack region */
if (_get_region_index_by_type(THREAD_STACK_REGION) == r_index) {
Expand Down Expand Up @@ -437,7 +435,7 @@ static int arm_mpu_init(struct device *arg)
SYS_LOG_DBG("total region count: %d", _get_num_regions());

/* Disable MPU */
ARM_MPU_DEV->ctrl = 0;
MPU->CTRL = 0;

/* Configure regions */
for (r_index = 0; r_index < mpu_config.num_regions; r_index++) {
Expand All @@ -449,7 +447,7 @@ static int arm_mpu_init(struct device *arg)
/* Enable MPU and use the default memory map as a
* background region for privileged software access.
*/
ARM_MPU_DEV->ctrl = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;

#if defined(CONFIG_APPLICATION_MEMORY)
u32_t index, size, region_attr;
Expand All @@ -470,7 +468,7 @@ static int arm_mpu_init(struct device *arg)
#if defined(CONFIG_CPU_CORTEX_M0PLUS) || \
defined(CONFIG_CPU_CORTEX_M3) || \
defined(CONFIG_CPU_CORTEX_M4)
__ASSERT((ARM_MPU_DEV->type & 0xFF00) >> 8 == 8,
__ASSERT((MPU->TYPE & 0xFF00) >> 8 == 8,
"Invalid number of MPU regions\n");
#endif
return 0;
Expand Down
93 changes: 59 additions & 34 deletions arch/arm/soc/arm/beetle/soc_mpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -11,61 +11,86 @@
* ARM MPU macro definitions required for SOCs
* which are not ARM CMSIS-compliant.
*/
#include <stdint.h>

#if defined(CONFIG_ARM_MPU)

#define __IM volatile const
#define __OM volatile
#define __IOM volatile

/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct {
__IM u32_t TYPE;
__IOM u32_t CTRL;
__IOM u32_t RNR;
__IOM u32_t RBAR;
__IOM u32_t RASR;
__IOM u32_t RBAR_A1;
__IOM u32_t RASR_A1;
__IOM u32_t RBAR_A2;
__IOM u32_t RASR_A2;
__IOM u32_t RBAR_A3;
__IOM u32_t RASR_A3;
} MPU_Type;

#define MPU ((MPU_Type *)0xE000ED90UL)

/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_PRIVDEFENA_Pos 2U
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
#define MPU_CTRL_ENABLE_Pos 0U
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
#define MPU_RNR_REGION_Pos 0U
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_ADDR_Pos 5U
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_VALID_Pos 4U
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)

#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
#define MPU_RBAR_REGION_Pos 0U
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_ATTRS_Pos 16U
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)

#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_XN_Pos 28U
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)

#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_AP_Pos 24U
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)

#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_TEX_Pos 19U
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)

#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_S_Pos 18U
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)

#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_C_Pos 17U
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)

#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_B_Pos 16U
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)

#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SRD_Pos 8U
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)

#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_SIZE_Pos 1U
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)

#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
#define MPU_RASR_ENABLE_Pos 0U
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)

#endif /* CONFIG_ARM_MPU */
30 changes: 0 additions & 30 deletions include/arch/arm/arch.h
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Original file line number Diff line number Diff line change
Expand Up @@ -258,36 +258,6 @@ extern "C" {
#ifdef CONFIG_ARM_MPU
#ifndef _ASMLANGUAGE
#include <arch/arm/cortex_m/mpu/arm_mpu.h>

#define K_MEM_PARTITION_P_NA_U_NA (NO_ACCESS | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RW_U_RW (P_RW_U_RW | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RW_U_RO (P_RW_U_RO | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RO_U_RO (P_RO_U_RO | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RO_U_NA (P_RO_U_NA | MPU_RASR_XN_Msk)

/* Execution-allowed attributes */
#define K_MEM_PARTITION_P_RWX_U_RWX (P_RW_U_RW)
#define K_MEM_PARTITION_P_RWX_U_RX (P_RW_U_RO)
#define K_MEM_PARTITION_P_RX_U_RX (P_RO_U_RO)

#define K_MEM_PARTITION_IS_WRITABLE(attr) \
({ \
int __is_writable__; \
switch (attr) { \
case P_RW_U_RW: \
case P_RW_U_RO: \
case P_RW_U_NA: \
__is_writable__ = 1; \
break; \
default: \
__is_writable__ = 0; \
} \
__is_writable__; \
})
#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
(!((attr) & (MPU_RASR_XN_Msk)))

#endif /* _ASMLANGUAGE */
#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
BUILD_ASSERT_MSG(!(((size) & ((size) - 1))) && (size) >= 32 && \
Expand Down
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