soc/intel_adsp: bump core count to four for TGPLP cAVS builds

With addition of separate intel_adsp_cavs25_tgph board to cover 2 core variants, we can now bump the core count to four cores for intel_adsp_cavs25 (used in Tiger Lake LP PCH). Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
zephyrproject-rtos · Feb 28, 2022 · ba02864 · ba02864
1 parent 8386e1f
commit ba02864
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig
@@ -19,3 +19,5 @@ CONFIG_CAVS_ICTL=y
 CONFIG_BOOTLOADER_SRAM_SIZE=192
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_CLEANUP_INTERMEDIATE_FILES=y
+
+CONFIG_MP_NUM_CPUS=4