simplicity_sdk: Update to 2024.12.0

Origin: Simplicity SDK
License: Zlib
URL: https://github.com/SiliconLabs/simplicity_sdk
Commit: 8627f8482564dc6d94b56512740a39d6f409a0eb
Purpose: HAL for Silicon Labs Series 2 devices

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>

simplicity_sdk/License.txt

@@ -1,6 +1,9 @@
 # Simplicity SDK Licensing terms
 
-Source code in this SDK is covered by one of several different licenses.
+Source code in this SDK is licensed to you under the terms of a default license
+from Silicon Laboratories Inc. This default license and exceptions to this 
+default licensing are set forth below.
+
 The default license is the Master Software License Agreement (MSLA) 
 (https://www.silabs.com/about-us/legal/master-software-license-agreement),
 which applies unless otherwise noted.

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h

@@ -135,6 +135,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h

@@ -36,6 +36,7 @@ extern "C" {
 #endif
 
 #include <stdint.h>
+#include "sl_code_classification.h"
 
 /***************************************************************************//**
  * @addtogroup Parts
@@ -165,6 +166,7 @@ void EUART0_TX_IRQHandler(void);         /**< EUART0_TX IRQ Handler */
 void FPUEH_IRQHandler(void);        /**< FPU IRQ Handler */
 #endif
 
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemHCLKGet(void);
 
 /**************************************************************************//**
@@ -181,6 +183,7 @@ uint32_t SystemHCLKGet(void);
  *   provided for CMSIS compliance and if a user modifies the the core clock
  *   outside the EMLIB CMU API.
  *****************************************************************************/
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 static __INLINE uint32_t SystemCoreClockGet(void)
 {
   return SystemHCLKGet();
@@ -200,23 +203,33 @@ static __INLINE uint32_t SystemCoreClockGet(void)
  *   provided for CMSIS compliance and if a user modifies the the core clock
  *   outside the EMLIB CMU API.
  *****************************************************************************/
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 static __INLINE void SystemCoreClockUpdate(void)
 {
   SystemHCLKGet();
 }
 
 void     SystemInit(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemHFRCODPLLClockGet(void);
 void     SystemHFRCODPLLClockSet(uint32_t freq);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemSYSCLKGet(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemMaxCoreClockGet(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemFSRCOClockGet(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemHFXOClockGet(void);
 void     SystemHFXOClockSet(uint32_t freq);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemCLKIN0Get(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemLFXOClockGet(void);
 void     SystemLFXOClockSet(uint32_t freq);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemLFRCOClockGet(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemULFRCOClockGet(void);
 
 /** @} End of group */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c

@@ -31,6 +31,15 @@
 #include <stdint.h>
 #include "em_device.h"
 
+#if defined(SL_COMPONENT_CATALOG_PRESENT)
+#include "sl_component_catalog.h"
+
+#endif
+#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT)
+#include "sl_clock_manager_oscillator_config.h"
+
+#endif
+
 /*******************************************************************************
  ******************************   DEFINES   ************************************
  ******************************************************************************/
@@ -64,7 +73,10 @@
 #endif
 
 // CLKIN0 input
-#if !defined(CLKIN0_FREQ)
+#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ)
+// Clock Manager takes control of this define when present.
+#define CLKIN0_FREQ    (SL_CLOCK_MANAGER_CLKIN0_FREQ)
+#elif !defined(CLKIN0_FREQ)
 #define CLKIN0_FREQ    (0UL)
 #endif
 
@@ -204,12 +216,11 @@ void SystemInit(void)
  *****************************************************************************/
 uint32_t SystemHFRCODPLLClockGet(void)
 {
-#if defined(BOOTLOADER_SYSTEM_NO_STATIC_MEMORY)
-  return HFRCODPLL_STARTUP_FREQ;
-#elif !defined(SYSTEM_NO_STATIC_MEMORY)
+#if !defined(SYSTEM_NO_STATIC_MEMORY)
   return SystemHFRCODPLLClock;
 #else
   uint32_t ret = 0UL;
+  CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0;
 
   // Get oscillator frequency band
   switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK)

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h

@@ -361,15 +361,15 @@ typedef struct syscfg_typedef{
 #define SYSCFG_IEN_FRCRAMERR2B_DEFAULT                     (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN         */
 
 /* Bit fields for SYSCFG CHIPREVHW */
-#define _SYSCFG_CHIPREVHW_RESETVALUE                       0x00010011UL                                /**< Default value for SYSCFG_CHIPREVHW          */
+#define _SYSCFG_CHIPREVHW_RESETVALUE                       0x00011011UL                                /**< Default value for SYSCFG_CHIPREVHW          */
 #define _SYSCFG_CHIPREVHW_MASK                             0xFF0FFFFFUL                                /**< Mask for SYSCFG_CHIPREVHW                   */
 #define _SYSCFG_CHIPREVHW_PARTNUMBER_SHIFT                 0                                           /**< Shift value for SYSCFG_PARTNUMBER           */
 #define _SYSCFG_CHIPREVHW_PARTNUMBER_MASK                  0xFFFUL                                     /**< Bit mask for SYSCFG_PARTNUMBER              */
 #define _SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT               0x00000011UL                                /**< Mode DEFAULT for SYSCFG_CHIPREVHW           */
 #define SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT                (_SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW   */
 #define _SYSCFG_CHIPREVHW_MINOR_SHIFT                      12                                          /**< Shift value for SYSCFG_MINOR                */
 #define _SYSCFG_CHIPREVHW_MINOR_MASK                       0xF000UL                                    /**< Bit mask for SYSCFG_MINOR                   */
-#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT                    0x00000000UL                                /**< Mode DEFAULT for SYSCFG_CHIPREVHW           */
+#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT                    0x00000001UL                                /**< Mode DEFAULT for SYSCFG_CHIPREVHW           */
 #define SYSCFG_CHIPREVHW_MINOR_DEFAULT                     (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12)     /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW   */
 #define _SYSCFG_CHIPREVHW_MAJOR_SHIFT                      16                                          /**< Shift value for SYSCFG_MAJOR                */
 #define _SYSCFG_CHIPREVHW_MAJOR_MASK                       0xF0000UL                                   /**< Bit mask for SYSCFG_MAJOR                   */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h

@@ -138,6 +138,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h

@@ -138,6 +138,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h

@@ -138,6 +138,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h

@@ -138,6 +138,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h

@@ -138,6 +138,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h

@@ -138,6 +138,7 @@ typedef enum IRQn{
  * @brief Processor and Core Peripheral Section
  *****************************************************************************/
 
+#define __CORTEXM                 1U      /**< Core architecture */
 #define __CM33_REV                0x0004U /**< Cortex-M33 Core revision */
 #define __DSP_PRESENT             1U      /**< Presence of DSP  */
 #define __FPU_PRESENT             1U      /**< Presence of FPU  */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h

@@ -36,6 +36,7 @@ extern "C" {
 #endif
 
 #include <stdint.h>
+#include "sl_code_classification.h"
 
 /***************************************************************************//**
  * @addtogroup Parts
@@ -168,6 +169,7 @@ void FPUEXH_IRQHandler(void);            /**< FPUEXH IRQ Handler */
 void FPUEH_IRQHandler(void);        /**< FPU IRQ Handler */
 #endif
 
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemHCLKGet(void);
 
 /**************************************************************************//**
@@ -184,6 +186,7 @@ uint32_t SystemHCLKGet(void);
  *   provided for CMSIS compliance and if a user modifies the the core clock
  *   outside the EMLIB CMU API.
  *****************************************************************************/
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 static __INLINE uint32_t SystemCoreClockGet(void)
 {
   return SystemHCLKGet();
@@ -203,23 +206,33 @@ static __INLINE uint32_t SystemCoreClockGet(void)
  *   provided for CMSIS compliance and if a user modifies the the core clock
  *   outside the EMLIB CMU API.
  *****************************************************************************/
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 static __INLINE void SystemCoreClockUpdate(void)
 {
   SystemHCLKGet();
 }
 
 void     SystemInit(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemHFRCODPLLClockGet(void);
 void     SystemHFRCODPLLClockSet(uint32_t freq);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemSYSCLKGet(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemMaxCoreClockGet(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemFSRCOClockGet(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemHFXOClockGet(void);
 void     SystemHFXOClockSet(uint32_t freq);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemCLKIN0Get(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemLFXOClockGet(void);
 void     SystemLFXOClockSet(uint32_t freq);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemLFRCOClockGet(void);
+SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL)
 uint32_t SystemULFRCOClockGet(void);
 
 /** @} End of group */

simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c

@@ -31,6 +31,15 @@
 #include <stdint.h>
 #include "em_device.h"
 
+#if defined(SL_COMPONENT_CATALOG_PRESENT)
+#include "sl_component_catalog.h"
+
+#endif
+#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT)
+#include "sl_clock_manager_oscillator_config.h"
+
+#endif
+
 /*******************************************************************************
  ******************************   DEFINES   ************************************
  ******************************************************************************/
@@ -64,7 +73,10 @@
 #endif
 
 // CLKIN0 input
-#if !defined(CLKIN0_FREQ)
+#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ)
+// Clock Manager takes control of this define when present.
+#define CLKIN0_FREQ    (SL_CLOCK_MANAGER_CLKIN0_FREQ)
+#elif !defined(CLKIN0_FREQ)
 #define CLKIN0_FREQ    (0UL)
 #endif
 
@@ -204,12 +216,11 @@ void SystemInit(void)
  *****************************************************************************/
 uint32_t SystemHFRCODPLLClockGet(void)
 {
-#if defined(BOOTLOADER_SYSTEM_NO_STATIC_MEMORY)
-  return HFRCODPLL_STARTUP_FREQ;
-#elif !defined(SYSTEM_NO_STATIC_MEMORY)
+#if !defined(SYSTEM_NO_STATIC_MEMORY)
   return SystemHFRCODPLLClock;
 #else
   uint32_t ret = 0UL;
+  CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0;
 
   // Get oscillator frequency band
   switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK)